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[mips][ias] Allow whitespace after commas in inlineasm*.ll tests.

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IAS always prints whitespace after a comma. NFC at the moment but this will
prevent failures when IAS is enabled.

llvm-svn: 253208
This commit is contained in:
Daniel Sanders 2015-11-16 14:14:59 +00:00
parent add8d5cbfa
commit d9971d4af4
4 changed files with 59 additions and 59 deletions
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36
test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
View File

@ -7,38 +7,38 @@ define i32 @main() nounwind {
entry:
; r with char
;CHECK: #APP
;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},23
;CHECK: #NO_APP
tail call i8 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind
;CHECK: #APP
;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
;CHECK: #NO_APP
tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind
; r with short
;CHECK: #APP
;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},13
;CHECK: #NO_APP
tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind
;CHECK: #APP
;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13
;CHECK: #NO_APP
tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind
; r with int
;CHECK: #APP
;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
;CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
;CHECK: #APP
;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
;CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind
; Now c with 1024: make sure register $25 is picked
; CHECK: #APP
; CHECK: addiu $25,${{[0-9]+}},1024
; CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
; CHECK: addiu $25, ${{[0-9]+}}, 1024
; CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind
; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
; after the inline expression for a mflo to pull the value out of lo.
; CHECK: #APP
; CHECK: mtlo ${{[0-9]+}}
; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}}
; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: #NO_APP
; CHECK-NEXT: mflo ${{[0-9]+}}
; CHECK-NEXT: mflo ${{[0-9]+}}
%bosco = alloca i32, align 4
call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
store volatile i32 %4, i32* %bosco, align 4
ret i32 0

4
test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
View File

@ -12,9 +12,9 @@ entry:
; r with long long
;CHECK: #APP
;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
;CHECK: #NO_APP
tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind
ret i32 0
}

46
test/CodeGen/Mips/inlineasm-operand-code.ll
View File

@ -12,9 +12,9 @@ define i32 @constraint_X() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_X:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ;
tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@ -23,9 +23,9 @@ define i32 @constraint_x() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_x:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffd
;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ;
tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@ -34,9 +34,9 @@ define i32 @constraint_d() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_d:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ;
tail call i32 asm sideeffect "addiu $0, $1, ${2:d}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@ -45,9 +45,9 @@ define i32 @constraint_m() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_m:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-4
;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ;
tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@ -56,15 +56,15 @@ define i32 @constraint_z() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_z:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ;
tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
; z with 0
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0
;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
; z with non-zero and the "r"(register) and "J"(integer zero) constraints
;CHECK_LITTLE_32: #APP
@ -100,9 +100,9 @@ define i32 @constraint_longlong() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_longlong:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},3
;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
;CHECK_LITTLE_32: #NO_APP
tail call i64 asm sideeffect "addiu $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
tail call i64 asm sideeffect "addiu $0, $1, $2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
ret i32 0
}
@ -114,7 +114,7 @@ entry:
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
; D, in big endian the source reg will also be 4 bytes into the long long
@ -123,11 +123,11 @@ entry:
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_BIG_32: #APP
;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
;CHECK_BIG_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
;CHECK_BIG_32: #NO_APP
%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
%trunc1 = trunc i64 %bosco to i32
tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
tail call i32 asm sideeffect "or $0, ${1:D}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
ret i32 0
}
@ -139,7 +139,7 @@ entry:
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
; L, in big endian the source reg will be 4 bytes into the long long
;CHECK_BIG_32-LABEL: constraint_L:
@ -147,11 +147,11 @@ entry:
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_BIG_32: #APP
;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
;CHECK_BIG_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
;CHECK_BIG_32: #NO_APP
%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
%trunc1 = trunc i64 %bosco to i32
tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
tail call i32 asm sideeffect "or $0, ${1:L}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
ret i32 0
}
@ -163,7 +163,7 @@ entry:
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
; M, in big endian the source reg will be 0 bytes into the long long
;CHECK_BIG_32-LABEL: constraint_M:
@ -171,10 +171,10 @@ entry:
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_BIG_32: #APP
;CHECK_BIG_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
;CHECK_BIG_32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
;CHECK_BIG_32: #NO_APP
%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
%trunc1 = trunc i64 %bosco to i32
tail call i32 asm sideeffect "or $0,${1:M},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
tail call i32 asm sideeffect "or $0, ${1:M}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
ret i32 0
}

32
test/CodeGen/Mips/inlineasm_constraint.ll
View File

@ -5,51 +5,51 @@ entry:
; First I with short
; CHECK: #APP
; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096
; CHECK: #NO_APP
tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i16 7, i16 4096) nounwind
; Then I with int
; CHECK: #APP
; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
; CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i32 7, i32 -3) nounwind
; Now J with 0
; CHECK: #APP
; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
; CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
tail call i32 asm sideeffect "addiu $0, $1, $2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
; Now K with 64
; CHECK: #APP
; CHECK: addu ${{[0-9]+}},${{[0-9]+}},64
; CHECK: addu ${{[0-9]+}}, ${{[0-9]+}}, 64
; CHECK: #NO_APP
tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
; Now L with 0x00100000
; CHECK: #APP
; CHECK: add ${{[0-9]+}},${{[0-9]+}},${{[0-9]+}}
; CHECK: add ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: #NO_APP
tail call i32 asm sideeffect "add $0,$1,$3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
tail call i32 asm sideeffect "add $0, $1, $3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
; Now N with -3
; CHECK: #APP
; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
; CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,N"(i32 7, i32 -3) nounwind
; Now O with -3
; CHECK: #APP
; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
; CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,O"(i32 7, i16 -3) nounwind
; Now P with 65535
; CHECK: #APP
; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},65535
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 65535
; CHECK: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,P"(i32 7, i32 65535) nounwind
ret i32 0
}