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[X86] Replace an APInt that is guaranteed to be 8-bits with just an 'unsigned'

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We're already mixing this APInt with other 'unsigned' variables. This allows us to use regular comparison operators instead of needing to use APInt::ult or APInt::uge. And it removes a later conversion from APInt to unsigned.

I might be adding another combine to this function and this will probably simplify the logic required for that.

llvm-svn: 347684
This commit is contained in:
Craig Topper 2018-11-27 18:24:56 +00:00
parent cfda8a97b4
commit d99e39cf74
1 changed files with 8 additions and 8 deletions
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16
lib/Target/X86/X86ISelLowering.cpp
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@ -35429,11 +35429,12 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
unsigned NumBitsPerElt = VT.getScalarSizeInBits(); unsigned NumBitsPerElt = VT.getScalarSizeInBits();
assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 && assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 &&
"Unexpected value type"); "Unexpected value type");
assert(N1.getValueType() == MVT::i8 && "Unexpected shift amount type");
// Out of range logical bit shifts are guaranteed to be zero. // Out of range logical bit shifts are guaranteed to be zero.
// Out of range arithmetic bit shifts splat the sign bit. // Out of range arithmetic bit shifts splat the sign bit.
APInt ShiftVal = cast<ConstantSDNode>(N1)->getAPIntValue(); unsigned ShiftVal = cast<ConstantSDNode>(N1)->getZExtValue();
if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt)) { if (ShiftVal >= NumBitsPerElt) {
if (LogicalShift) if (LogicalShift)
return DAG.getConstant(0, SDLoc(N), VT); return DAG.getConstant(0, SDLoc(N), VT);
else else
@ -35460,12 +35461,12 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
N1 == N0.getOperand(1)) { N1 == N0.getOperand(1)) {
SDValue N00 = N0.getOperand(0); SDValue N00 = N0.getOperand(0);
unsigned NumSignBits = DAG.ComputeNumSignBits(N00); unsigned NumSignBits = DAG.ComputeNumSignBits(N00);
if (ShiftVal.ult(NumSignBits)) if (ShiftVal < NumSignBits)
return N00; return N00;
} }
// We can decode 'whole byte' logical bit shifts as shuffles. // We can decode 'whole byte' logical bit shifts as shuffles.
if (LogicalShift && (ShiftVal.getZExtValue() % 8) == 0) { if (LogicalShift && (ShiftVal % 8) == 0) {
SDValue Op(N, 0); SDValue Op(N, 0);
if (SDValue Res = combineX86ShufflesRecursively( if (SDValue Res = combineX86ShufflesRecursively(
{Op}, 0, Op, {0}, {}, /*Depth*/ 1, {Op}, 0, Op, {0}, {}, /*Depth*/ 1,
@ -35480,14 +35481,13 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
getTargetConstantBitsFromNode(N0, NumBitsPerElt, UndefElts, EltBits)) { getTargetConstantBitsFromNode(N0, NumBitsPerElt, UndefElts, EltBits)) {
assert(EltBits.size() == VT.getVectorNumElements() && assert(EltBits.size() == VT.getVectorNumElements() &&
"Unexpected shift value type"); "Unexpected shift value type");
unsigned ShiftImm = ShiftVal.getZExtValue();
for (APInt &Elt : EltBits) { for (APInt &Elt : EltBits) {
if (X86ISD::VSHLI == Opcode) if (X86ISD::VSHLI == Opcode)
Elt <<= ShiftImm; Elt <<= ShiftVal;
else if (X86ISD::VSRAI == Opcode) else if (X86ISD::VSRAI == Opcode)
Elt.ashrInPlace(ShiftImm); Elt.ashrInPlace(ShiftVal);
else else
Elt.lshrInPlace(ShiftImm); Elt.lshrInPlace(ShiftVal);
} }
return getConstVector(EltBits, UndefElts, VT.getSimpleVT(), DAG, SDLoc(N)); return getConstVector(EltBits, UndefElts, VT.getSimpleVT(), DAG, SDLoc(N));
} }