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Allow explicit %reg0 operands beyond what the .td file describes.

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ARM uses these to indicate predicates.

llvm-svn: 91922
This commit is contained in:
Jakob Stoklund Olesen 2009-12-22 21:48:20 +00:00
parent 237cb134ed
commit d9cec1fbf7
1 changed files with 2 additions and 1 deletions
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3
lib/CodeGen/MachineVerifier.cpp
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@ -553,7 +553,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
report("Explicit operand marked as implicit", MO, MONum);
}
} else {
if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
// ARM adds %reg0 operands to indicate predicates. We'll allow that.
if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
report("Extra explicit operand on non-variadic instruction", MO, MONum);
}