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Clean up whitespace.
llvm-svn: 138833
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1e8c335302
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@ -113,7 +113,7 @@ public:
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/// immediate Thumb2 direct branch target.
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uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
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/// branch target.
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uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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@ -508,9 +508,9 @@ static bool HasConditionalBranch(const MCInst &MI) {
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for (int i = 0; i < NumOp-1; ++i) {
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const MCOperand &MCOp1 = MI.getOperand(i);
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const MCOperand &MCOp2 = MI.getOperand(i + 1);
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if (MCOp1.isImm() && MCOp2.isReg() &&
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if (MCOp1.isImm() && MCOp2.isReg() &&
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(MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
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if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
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if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
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return true;
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}
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}
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@ -538,10 +538,10 @@ getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand MO = MI.getOperand(OpIdx);
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if (MO.isExpr()) {
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if (HasConditionalBranch(MI))
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if (HasConditionalBranch(MI))
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return ::getBranchTargetOpValue(MI, OpIdx,
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ARM::fixup_arm_condbranch, Fixups);
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return ::getBranchTargetOpValue(MI, OpIdx,
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return ::getBranchTargetOpValue(MI, OpIdx,
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ARM::fixup_arm_uncondbranch, Fixups);
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}
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@ -553,10 +553,10 @@ getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand MO = MI.getOperand(OpIdx);
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if (MO.isExpr()) {
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if (HasConditionalBranch(MI))
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if (HasConditionalBranch(MI))
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return ::getBranchTargetOpValue(MI, OpIdx,
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ARM::fixup_arm_condbranch, Fixups);
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return ::getBranchTargetOpValue(MI, OpIdx,
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return ::getBranchTargetOpValue(MI, OpIdx,
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ARM::fixup_arm_uncondbranch, Fixups);
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}
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@ -1350,7 +1350,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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Size = Desc.getSize();
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else
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llvm_unreachable("Unexpected instruction size!");
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uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
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// Thumb 32-bit wide instructions need to emit the high order halfword
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// first.
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