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[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook
After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
This commit is contained in:
QingShan Zhang
parent
88b4c7ca50
commit
da451ad14d
@ -3996,3 +3996,59 @@ unsigned PPCInstrInfo::reduceLoopCount(
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return LoopCountReg;
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}
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// Return true if get the base operand, byte offset of an instruction and the
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// memory width. Width is the size of memory that is being loaded/stored.
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bool PPCInstrInfo::getMemOperandWithOffsetWidth(
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const MachineInstr &LdSt,
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const MachineOperand *&BaseReg,
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int64_t &Offset,
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unsigned &Width,
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const TargetRegisterInfo *TRI) const {
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assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
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// Handle only loads/stores with base register followed by immediate offset.
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if (LdSt.getNumExplicitOperands() != 3)
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return false;
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if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
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return false;
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if (!LdSt.hasOneMemOperand())
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return false;
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Width = (*LdSt.memoperands_begin())->getSize();
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Offset = LdSt.getOperand(1).getImm();
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BaseReg = &LdSt.getOperand(2);
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return true;
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}
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bool PPCInstrInfo::areMemAccessesTriviallyDisjoint(
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const MachineInstr &MIa, const MachineInstr &MIb,
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AliasAnalysis * /*AA*/) const {
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assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
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assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
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if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
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MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
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return false;
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// Retrieve the base register, offset from the base register and width. Width
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// is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
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// base registers are identical, and the offset of a lower memory access +
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// the width doesn't overlap the offset of a higher memory access,
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// then the memory accesses are different.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
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int64_t OffsetA = 0, OffsetB = 0;
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unsigned int WidthA = 0, WidthB = 0;
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if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
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getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
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if (BaseOpA->isIdenticalTo(*BaseOpB)) {
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int LowOffset = std::min(OffsetA, OffsetB);
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int HighOffset = std::max(OffsetA, OffsetB);
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int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
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if (LowOffset + LowWidth <= HighOffset)
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return true;
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}
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}
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return false;
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}
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@ -357,6 +357,22 @@ public:
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unsigned SrcReg2, int Mask, int Value,
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const MachineRegisterInfo *MRI) const override;
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/// Return true if get the base operand, byte offset of an instruction and
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/// the memory width. Width is the size of memory that is being
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/// loaded/stored (e.g. 1, 2, 4, 8).
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bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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const MachineOperand *&BaseOp,
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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/// Return true if two MIs access different memory addresses and false
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/// otherwise
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bool
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areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb,
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AliasAnalysis *AA = nullptr) const override;
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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@ -12,26 +12,26 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
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; CHECK-NEXT: lis 3, .LCPI0_0@ha
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; CHECK-NEXT: stw 12, 408(1)
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; CHECK-NEXT: stfd 2, 376(1)
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; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 1, 384(1)
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; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 2, 376(1)
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; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
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; CHECK-NEXT: stfd 1, 384(1)
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; CHECK-NEXT: lwz 4, 380(1)
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; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
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; CHECK-NEXT: lwz 3, 384(1)
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; CHECK-NEXT: stw 4, 396(1)
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: lwz 4, 376(1)
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; CHECK-NEXT: fcmpu 1, 1, 27
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; CHECK-NEXT: crand 20, 6, 0
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; CHECK-NEXT: stw 4, 396(1)
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; CHECK-NEXT: cror 20, 4, 20
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; CHECK-NEXT: lwz 4, 376(1)
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; CHECK-NEXT: stw 4, 392(1)
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; CHECK-NEXT: stw 3, 400(1)
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; CHECK-NEXT: lwz 4, 388(1)
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; CHECK-NEXT: stw 4, 404(1)
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; CHECK-NEXT: lwz 3, 384(1)
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; CHECK-NEXT: stw 3, 400(1)
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; CHECK-NEXT: bc 4, 20, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %bb5
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; CHECK-NEXT: li 3, 0
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@ -39,50 +39,50 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: b .LBB0_16
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; CHECK-NEXT: .LBB0_2: # %bb1
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; CHECK-NEXT: lfd 0, 400(1)
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; CHECK-NEXT: lis 3, 15856
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; CHECK-NEXT: stw 3, 336(1)
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; CHECK-NEXT: lfd 1, 392(1)
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; CHECK-NEXT: li 29, 0
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; CHECK-NEXT: lis 3, 15856
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; CHECK-NEXT: stfd 0, 304(1)
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; CHECK-NEXT: stfd 1, 296(1)
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; CHECK-NEXT: stw 29, 340(1)
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; CHECK-NEXT: stw 3, 336(1)
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; CHECK-NEXT: stw 29, 332(1)
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; CHECK-NEXT: stw 29, 328(1)
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; CHECK-NEXT: lwz 3, 308(1)
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; CHECK-NEXT: stfd 1, 296(1)
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; CHECK-NEXT: lfd 3, 336(1)
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; CHECK-NEXT: lfd 4, 328(1)
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; CHECK-NEXT: stw 3, 324(1)
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; CHECK-NEXT: lwz 3, 304(1)
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; CHECK-NEXT: stw 3, 320(1)
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; CHECK-NEXT: lwz 3, 300(1)
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; CHECK-NEXT: lfd 31, 320(1)
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; CHECK-NEXT: stw 3, 316(1)
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; CHECK-NEXT: fmr 1, 31
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; CHECK-NEXT: lwz 3, 296(1)
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; CHECK-NEXT: stw 3, 312(1)
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; CHECK-NEXT: lfd 31, 320(1)
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; CHECK-NEXT: lfd 30, 312(1)
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; CHECK-NEXT: lfd 3, 336(1)
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; CHECK-NEXT: lfd 4, 328(1)
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; CHECK-NEXT: fmr 1, 31
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; CHECK-NEXT: fmr 2, 30
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; CHECK-NEXT: bl __gcc_qmul@PLT
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; CHECK-NEXT: lis 3, 16864
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; CHECK-NEXT: stfd 1, 280(1)
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; CHECK-NEXT: fmr 29, 1
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; CHECK-NEXT: stfd 2, 288(1)
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; CHECK-NEXT: fmr 28, 2
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; CHECK-NEXT: stw 29, 372(1)
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; CHECK-NEXT: stw 3, 368(1)
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; CHECK-NEXT: stfd 2, 288(1)
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; CHECK-NEXT: stw 29, 372(1)
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; CHECK-NEXT: stw 29, 364(1)
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; CHECK-NEXT: stw 29, 360(1)
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; CHECK-NEXT: fmr 29, 1
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; CHECK-NEXT: lwz 3, 284(1)
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; CHECK-NEXT: fmr 28, 2
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; CHECK-NEXT: lfd 3, 368(1)
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; CHECK-NEXT: lfd 4, 360(1)
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; CHECK-NEXT: stw 3, 356(1)
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; CHECK-NEXT: lwz 3, 280(1)
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; CHECK-NEXT: stw 3, 352(1)
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; CHECK-NEXT: lwz 3, 292(1)
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; CHECK-NEXT: lfd 1, 352(1)
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; CHECK-NEXT: stw 3, 348(1)
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; CHECK-NEXT: lwz 3, 288(1)
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; CHECK-NEXT: stw 3, 344(1)
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; CHECK-NEXT: lfd 3, 368(1)
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; CHECK-NEXT: lfd 4, 360(1)
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; CHECK-NEXT: lfd 1, 352(1)
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; CHECK-NEXT: lfd 2, 344(1)
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: mffs 0
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@ -102,8 +102,8 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: lfs 1, .LCPI0_1@l(3)
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; CHECK-NEXT: fctiwz 0, 0
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; CHECK-NEXT: stfd 0, 152(1)
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; CHECK-NEXT: fcmpu 1, 29, 1
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; CHECK-NEXT: lwz 3, 164(1)
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; CHECK-NEXT: fcmpu 1, 29, 1
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; CHECK-NEXT: lwz 4, 156(1)
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: cror 20, 5, 20
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@ -120,25 +120,25 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: bl __floatditf@PLT
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; CHECK-NEXT: lis 3, 17392
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; CHECK-NEXT: stfd 1, 208(1)
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; CHECK-NEXT: fmr 29, 1
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; CHECK-NEXT: stfd 2, 200(1)
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; CHECK-NEXT: fmr 28, 2
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; CHECK-NEXT: stw 29, 244(1)
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; CHECK-NEXT: stw 3, 240(1)
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; CHECK-NEXT: cmpwi 2, 30, 0
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; CHECK-NEXT: stfd 2, 200(1)
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; CHECK-NEXT: stw 29, 244(1)
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; CHECK-NEXT: stw 29, 236(1)
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; CHECK-NEXT: stw 29, 232(1)
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; CHECK-NEXT: fmr 29, 1
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; CHECK-NEXT: lwz 3, 212(1)
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; CHECK-NEXT: fmr 28, 2
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; CHECK-NEXT: lfd 3, 240(1)
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; CHECK-NEXT: lfd 4, 232(1)
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; CHECK-NEXT: cmpwi 2, 30, 0
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; CHECK-NEXT: stw 3, 228(1)
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; CHECK-NEXT: lwz 3, 208(1)
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; CHECK-NEXT: stw 3, 224(1)
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; CHECK-NEXT: lwz 3, 204(1)
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; CHECK-NEXT: lfd 1, 224(1)
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; CHECK-NEXT: stw 3, 220(1)
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; CHECK-NEXT: lwz 3, 200(1)
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; CHECK-NEXT: stw 3, 216(1)
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; CHECK-NEXT: lfd 3, 240(1)
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; CHECK-NEXT: lfd 4, 232(1)
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; CHECK-NEXT: lfd 1, 224(1)
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; CHECK-NEXT: lfd 2, 216(1)
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; CHECK-NEXT: bl __gcc_qadd@PLT
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; CHECK-NEXT: blt 2, .LBB0_7
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@ -150,60 +150,60 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: fmr 1, 29
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; CHECK-NEXT: .LBB0_9: # %bb1
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; CHECK-NEXT: stfd 1, 184(1)
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; CHECK-NEXT: fmr 1, 31
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; CHECK-NEXT: stfd 2, 192(1)
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; CHECK-NEXT: fmr 2, 30
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; CHECK-NEXT: fmr 1, 31
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; CHECK-NEXT: lwz 3, 188(1)
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; CHECK-NEXT: fmr 2, 30
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; CHECK-NEXT: stw 3, 260(1)
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; CHECK-NEXT: lwz 3, 184(1)
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; CHECK-NEXT: stw 3, 256(1)
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; CHECK-NEXT: lwz 3, 196(1)
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; CHECK-NEXT: lfd 3, 256(1)
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; CHECK-NEXT: stw 3, 252(1)
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; CHECK-NEXT: lwz 3, 192(1)
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; CHECK-NEXT: stw 3, 248(1)
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; CHECK-NEXT: lfd 3, 256(1)
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; CHECK-NEXT: lfd 4, 248(1)
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: stfd 2, 176(1)
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: stfd 1, 168(1)
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; CHECK-NEXT: fcmpu 1, 1, 27
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: lwz 3, 180(1)
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; CHECK-NEXT: fcmpu 1, 1, 27
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: cror 21, 5, 7
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; CHECK-NEXT: cror 20, 21, 20
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; CHECK-NEXT: stw 3, 268(1)
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; CHECK-NEXT: cror 20, 21, 20
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; CHECK-NEXT: lwz 3, 176(1)
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; CHECK-NEXT: stw 3, 264(1)
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; CHECK-NEXT: lwz 3, 172(1)
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; CHECK-NEXT: lfd 30, 264(1)
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; CHECK-NEXT: stw 3, 276(1)
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; CHECK-NEXT: lwz 3, 168(1)
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; CHECK-NEXT: stw 3, 272(1)
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; CHECK-NEXT: lfd 30, 264(1)
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; CHECK-NEXT: lfd 31, 272(1)
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; CHECK-NEXT: bc 12, 20, .LBB0_13
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; CHECK-NEXT: # %bb.10: # %bb2
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; CHECK-NEXT: fneg 29, 30
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; CHECK-NEXT: fneg 28, 31
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; CHECK-NEXT: li 29, 0
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; CHECK-NEXT: lis 3, 16864
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; CHECK-NEXT: stfd 28, 48(1)
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; CHECK-NEXT: stfd 29, 40(1)
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; CHECK-NEXT: stw 29, 84(1)
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; CHECK-NEXT: lis 3, 16864
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; CHECK-NEXT: stw 3, 80(1)
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; CHECK-NEXT: fneg 29, 30
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; CHECK-NEXT: lwz 3, 52(1)
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; CHECK-NEXT: stfd 29, 40(1)
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; CHECK-NEXT: li 29, 0
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; CHECK-NEXT: stw 29, 84(1)
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; CHECK-NEXT: stw 29, 76(1)
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; CHECK-NEXT: stw 29, 72(1)
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; CHECK-NEXT: lwz 3, 52(1)
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; CHECK-NEXT: stw 3, 68(1)
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; CHECK-NEXT: lfd 3, 80(1)
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; CHECK-NEXT: lfd 4, 72(1)
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; CHECK-NEXT: lwz 3, 48(1)
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; CHECK-NEXT: stw 3, 64(1)
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; CHECK-NEXT: lwz 3, 44(1)
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; CHECK-NEXT: lfd 1, 64(1)
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; CHECK-NEXT: stw 3, 60(1)
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; CHECK-NEXT: lwz 3, 40(1)
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; CHECK-NEXT: stw 3, 56(1)
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; CHECK-NEXT: lfd 3, 80(1)
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; CHECK-NEXT: lfd 4, 72(1)
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; CHECK-NEXT: lfd 1, 64(1)
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; CHECK-NEXT: lfd 2, 56(1)
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: mffs 0
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@ -225,8 +225,8 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: fcmpu 0, 30, 0
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; CHECK-NEXT: fctiwz 2, 2
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; CHECK-NEXT: stfd 2, 24(1)
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; CHECK-NEXT: fcmpu 1, 31, 1
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; CHECK-NEXT: lwz 3, 36(1)
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; CHECK-NEXT: fcmpu 1, 31, 1
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; CHECK-NEXT: lwz 4, 28(1)
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; CHECK-NEXT: crandc 20, 6, 1
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; CHECK-NEXT: cror 20, 4, 20
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@ -240,25 +240,25 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: subfe 3, 29, 30
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; CHECK-NEXT: b .LBB0_16
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; CHECK-NEXT: .LBB0_13: # %bb3
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: lis 4, 16864
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; CHECK-NEXT: stfd 31, 112(1)
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; CHECK-NEXT: stfd 30, 104(1)
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: stw 3, 148(1)
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; CHECK-NEXT: stw 4, 144(1)
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; CHECK-NEXT: stw 3, 140(1)
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; CHECK-NEXT: stw 3, 136(1)
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; CHECK-NEXT: stfd 30, 104(1)
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; CHECK-NEXT: lis 4, 16864
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; CHECK-NEXT: lwz 3, 116(1)
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; CHECK-NEXT: stw 4, 144(1)
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; CHECK-NEXT: lfd 4, 136(1)
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; CHECK-NEXT: stw 3, 132(1)
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; CHECK-NEXT: lfd 3, 144(1)
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; CHECK-NEXT: lwz 3, 112(1)
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; CHECK-NEXT: stw 3, 128(1)
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; CHECK-NEXT: lwz 3, 108(1)
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; CHECK-NEXT: lfd 1, 128(1)
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; CHECK-NEXT: stw 3, 124(1)
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; CHECK-NEXT: lwz 3, 104(1)
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; CHECK-NEXT: stw 3, 120(1)
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; CHECK-NEXT: lfd 3, 144(1)
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; CHECK-NEXT: lfd 4, 136(1)
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; CHECK-NEXT: lfd 1, 128(1)
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; CHECK-NEXT: lfd 2, 120(1)
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: mffs 0
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@ -280,8 +280,8 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: fcmpu 0, 30, 0
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; CHECK-NEXT: fctiwz 2, 2
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; CHECK-NEXT: stfd 2, 88(1)
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; CHECK-NEXT: fcmpu 1, 31, 1
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; CHECK-NEXT: lwz 3, 100(1)
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; CHECK-NEXT: fcmpu 1, 31, 1
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; CHECK-NEXT: lwz 4, 92(1)
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: cror 20, 5, 20
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@ -744,6 +744,7 @@ define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
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; CHECK-NEXT: stb r4, 9(r5)
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; CHECK-NEXT: rldicl r4, r7, 32, 56
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; CHECK-NEXT: rldicl r6, r7, 8, 56
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; CHECK-NEXT: stb r3, 12(r5)
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; CHECK-NEXT: stb r4, 0(r5)
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; CHECK-NEXT: rldicl r4, r7, 16, 56
|
||||
; CHECK-NEXT: stb r6, 3(r5)
|
||||
@ -756,7 +757,6 @@ define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
|
||||
; CHECK-NEXT: rldicl r4, r7, 24, 56
|
||||
; CHECK-NEXT: stb r6, 10(r5)
|
||||
; CHECK-NEXT: stb r4, 11(r5)
|
||||
; CHECK-NEXT: stb r3, 12(r5)
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: test_13_consecutive_stores_of_bytes:
|
||||
|
||||
@ -82,6 +82,7 @@ define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
|
||||
align 16 %a) {
|
||||
; CHECK-LABEL: testStruct_03:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK: lxv v2, 128(r1)
|
||||
; CHECK-DAG: std r10, 88(r1)
|
||||
; CHECK-DAG: std r9, 80(r1)
|
||||
; CHECK-DAG: std r8, 72(r1)
|
||||
@ -90,11 +91,11 @@ define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
|
||||
; CHECK-DAG: std r5, 48(r1)
|
||||
; CHECK-DAG: std r4, 40(r1)
|
||||
; CHECK-DAG: std r3, 32(r1)
|
||||
; CHECK-NEXT: lxv v2, 128(r1)
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
; CHECK-BE-LABEL: testStruct_03:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE: lxv v2, 144(r1)
|
||||
; CHECK-BE-DAG: std r10, 104(r1)
|
||||
; CHECK-BE-DAG: std r9, 96(r1)
|
||||
; CHECK-BE-DAG: std r8, 88(r1)
|
||||
@ -103,7 +104,6 @@ define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
|
||||
; CHECK-BE-DAG: std r5, 64(r1)
|
||||
; CHECK-BE-DAG: std r4, 56(r1)
|
||||
; CHECK-BE-DAG: std r3, 48(r1)
|
||||
; CHECK-BE-NEXT: lxv v2, 144(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
entry:
|
||||
%a7 = getelementptr inbounds %struct.With9fp128params,
|
||||
@ -256,28 +256,28 @@ entry:
|
||||
define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
|
||||
; CHECK-LABEL: testNestedAggregate:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-DAG: std r10, 88(r1)
|
||||
; CHECK-DAG: std r9, 80(r1)
|
||||
; CHECK-DAG: std r8, 72(r1)
|
||||
; CHECK-DAG: std r7, 64(r1)
|
||||
; CHECK: lxv v2, 64(r1)
|
||||
; CHECK-DAG: std r10, 88(r1)
|
||||
; CHECK-DAG: std r9, 80(r1)
|
||||
; CHECK-DAG: std r6, 56(r1)
|
||||
; CHECK-DAG: std r5, 48(r1)
|
||||
; CHECK-DAG: std r4, 40(r1)
|
||||
; CHECK-DAG: std r3, 32(r1)
|
||||
; CHECK-NEXT: lxv v2, 64(r1)
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
; CHECK-BE-LABEL: testNestedAggregate:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE-DAG: std r8, 88(r1)
|
||||
; CHECK-BE-DAG: std r7, 80(r1)
|
||||
; CHECK-BE-NEXT: lxv v2, 80(r1)
|
||||
; CHECK-BE-DAG: std r10, 104(r1)
|
||||
; CHECK-BE-DAG: std r9, 96(r1)
|
||||
; CHECK-BE-DAG: std r6, 72(r1)
|
||||
; CHECK-BE-DAG: std r5, 64(r1)
|
||||
; CHECK-BE-DAG: std r4, 56(r1)
|
||||
; CHECK-BE-DAG: std r3, 48(r1)
|
||||
; CHECK-BE-NEXT: lxv v2, 80(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
entry:
|
||||
%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
|
||||
; BE-LABEL: test_large_vec_vaarg:
|
||||
; BE: # %bb.0:
|
||||
; BE-NEXT: ld 3, -8(1)
|
||||
; BE-NEXT: std 4, 56(1)
|
||||
; BE-NEXT: std 5, 64(1)
|
||||
; BE-NEXT: std 6, 72(1)
|
||||
@ -12,7 +13,6 @@ define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
|
||||
; BE-NEXT: std 8, 88(1)
|
||||
; BE-NEXT: std 9, 96(1)
|
||||
; BE-NEXT: std 10, 104(1)
|
||||
; BE-NEXT: ld 3, -8(1)
|
||||
; BE-NEXT: addi 3, 3, 15
|
||||
; BE-NEXT: rldicr 3, 3, 0, 59
|
||||
; BE-NEXT: addi 4, 3, 16
|
||||
@ -27,16 +27,16 @@ define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
|
||||
;
|
||||
; LE-LABEL: test_large_vec_vaarg:
|
||||
; LE: # %bb.0:
|
||||
; LE-NEXT: ld 3, -8(1)
|
||||
; LE-NEXT: std 4, 40(1)
|
||||
; LE-NEXT: std 5, 48(1)
|
||||
; LE-NEXT: std 6, 56(1)
|
||||
; LE-NEXT: std 7, 64(1)
|
||||
; LE-NEXT: addi 3, 3, 15
|
||||
; LE-NEXT: rldicr 3, 3, 0, 59
|
||||
; LE-NEXT: std 8, 72(1)
|
||||
; LE-NEXT: std 9, 80(1)
|
||||
; LE-NEXT: std 10, 88(1)
|
||||
; LE-NEXT: ld 3, -8(1)
|
||||
; LE-NEXT: addi 3, 3, 15
|
||||
; LE-NEXT: rldicr 3, 3, 0, 59
|
||||
; LE-NEXT: addi 4, 3, 31
|
||||
; LE-NEXT: addi 5, 3, 16
|
||||
; LE-NEXT: rldicr 4, 4, 0, 59
|
||||
|
||||
@ -16,10 +16,10 @@ entry:
|
||||
; left for long double type (4 registers in soft float mode). Instead in r8 register this
|
||||
; argument put on stack.
|
||||
; CHECK-NOT: mr 8, 4
|
||||
; CHECK: stw 7, 20(1)
|
||||
; CHECK: stw 6, 16(1)
|
||||
; CHECK: stw 5, 12(1)
|
||||
; CHECK: stw 4, 8(1)
|
||||
; CHECK: stw 7, 20(1)
|
||||
|
||||
declare i32 @printf(i8* nocapture readonly, ...)
|
||||
|
||||
|
||||
19
test/CodeGen/PowerPC/scheduling-mem-dependency.ll
Normal file
19
test/CodeGen/PowerPC/scheduling-mem-dependency.ll
Normal file
@ -0,0 +1,19 @@
|
||||
; REQUIRES: asserts
|
||||
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
|
||||
|
||||
define i64 @store_disjoint_memory(i64* nocapture %P, i64 %v) {
|
||||
entry:
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_disjoint_memory:%bb.0
|
||||
; CHECK:SU(2): STD renamable $x4, 24, renamable $x5 :: (store 8 into %ir.arrayidx)
|
||||
; CHECK-NOT: Successors:
|
||||
; CHECK-NOT: SU(3): Ord Latency=0 Memory
|
||||
; CHECK:SU(3): STD renamable $x4, 16, renamable $x5 :: (store 8 into %ir.arrayidx1)
|
||||
; CHECK: Predecessors:
|
||||
; CHECK-NOT: SU(2): Ord Latency=0 Memory
|
||||
%arrayidx = getelementptr inbounds i64, i64* %P, i64 3
|
||||
store i64 %v, i64* %arrayidx
|
||||
%arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
|
||||
store i64 %v, i64* %arrayidx1
|
||||
ret i64 %v
|
||||
}
|
||||
@ -8,25 +8,29 @@ define i8* @test1(i8** %foo) nounwind {
|
||||
; P32-LABEL: test1:
|
||||
; P32: # %bb.0:
|
||||
; P32-NEXT: lbz r4, 0(r3)
|
||||
; P32-NEXT: addi r5, r4, 1
|
||||
; P32-NEXT: stb r5, 0(r3)
|
||||
; P32-NEXT: cmpwi r4, 8
|
||||
; P32-NEXT: lwz r5, 4(r3)
|
||||
; P32-NEXT: lwz r6, 8(r3)
|
||||
; P32-NEXT: addi r7, r4, 1
|
||||
; P32-NEXT: stb r7, 0(r3)
|
||||
; P32-NEXT: addi r7, r5, 4
|
||||
; P32-NEXT: cmpwi r4, 8
|
||||
; P32-NEXT: slwi r4, r4, 2
|
||||
; P32-NEXT: addi r6, r5, 4
|
||||
; P32-NEXT: bc 12, lt, .LBB0_1
|
||||
; P32-NEXT: b .LBB0_2
|
||||
; P32-NEXT: .LBB0_1:
|
||||
; P32-NEXT: addi r6, r5, 0
|
||||
; P32-NEXT: add r4, r6, r4
|
||||
; P32-NEXT: bc 12, lt, .LBB0_2
|
||||
; P32-NEXT: # %bb.1:
|
||||
; P32-NEXT: ori r6, r7, 0
|
||||
; P32-NEXT: b .LBB0_3
|
||||
; P32-NEXT: .LBB0_2:
|
||||
; P32-NEXT: addi r6, r5, 0
|
||||
; P32-NEXT: .LBB0_3:
|
||||
; P32-NEXT: stw r6, 4(r3)
|
||||
; P32-NEXT: lwz r3, 8(r3)
|
||||
; P32-NEXT: add r3, r3, r4
|
||||
; P32-NEXT: bc 12, lt, .LBB0_4
|
||||
; P32-NEXT: # %bb.3:
|
||||
; P32-NEXT: bc 12, lt, .LBB0_5
|
||||
; P32-NEXT: # %bb.4:
|
||||
; P32-NEXT: ori r3, r5, 0
|
||||
; P32-NEXT: b .LBB0_4
|
||||
; P32-NEXT: .LBB0_4:
|
||||
; P32-NEXT: b .LBB0_6
|
||||
; P32-NEXT: .LBB0_5:
|
||||
; P32-NEXT: addi r3, r4, 0
|
||||
; P32-NEXT: .LBB0_6:
|
||||
; P32-NEXT: lwz r3, 0(r3)
|
||||
; P32-NEXT: blr
|
||||
;
|
||||
|
||||
@ -67,13 +67,13 @@ define <2 x i64> @getsmaxi64(<2 x i64> %a, <2 x i64> %b) {
|
||||
; NOP8VEC-NEXT: stxvd2x 1, 0, 4
|
||||
; NOP8VEC-NEXT: ld 3, -24(1)
|
||||
; NOP8VEC-NEXT: ld 4, -40(1)
|
||||
; NOP8VEC-NEXT: ld 6, -48(1)
|
||||
; NOP8VEC-NEXT: cmpd 4, 3
|
||||
; NOP8VEC-NEXT: li 3, 0
|
||||
; NOP8VEC-NEXT: li 4, -1
|
||||
; NOP8VEC-NEXT: isel 5, 4, 3, 1
|
||||
; NOP8VEC-NEXT: std 5, -8(1)
|
||||
; NOP8VEC-NEXT: ld 5, -32(1)
|
||||
; NOP8VEC-NEXT: ld 6, -48(1)
|
||||
; NOP8VEC-NEXT: cmpd 6, 5
|
||||
; NOP8VEC-NEXT: isel 3, 4, 3, 1
|
||||
; NOP8VEC-NEXT: std 3, -16(1)
|
||||
@ -184,13 +184,13 @@ define <2 x i64> @getsmini64(<2 x i64> %a, <2 x i64> %b) {
|
||||
; NOP8VEC-NEXT: stxvd2x 1, 0, 4
|
||||
; NOP8VEC-NEXT: ld 3, -24(1)
|
||||
; NOP8VEC-NEXT: ld 4, -40(1)
|
||||
; NOP8VEC-NEXT: ld 6, -48(1)
|
||||
; NOP8VEC-NEXT: cmpd 4, 3
|
||||
; NOP8VEC-NEXT: li 3, 0
|
||||
; NOP8VEC-NEXT: li 4, -1
|
||||
; NOP8VEC-NEXT: isel 5, 4, 3, 0
|
||||
; NOP8VEC-NEXT: std 5, -8(1)
|
||||
; NOP8VEC-NEXT: ld 5, -32(1)
|
||||
; NOP8VEC-NEXT: ld 6, -48(1)
|
||||
; NOP8VEC-NEXT: cmpd 6, 5
|
||||
; NOP8VEC-NEXT: isel 3, 4, 3, 0
|
||||
; NOP8VEC-NEXT: std 3, -16(1)
|
||||
|
||||
@ -802,9 +802,9 @@ define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: ld r3, -24(r1)
|
||||
; CHECK-NEXT: ld r4, -40(r1)
|
||||
; CHECK-NEXT: add r3, r4, r3
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: std r3, -8(r1)
|
||||
; CHECK-NEXT: ld r3, -32(r1)
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: add r3, r4, r3
|
||||
; CHECK-NEXT: std r3, -16(r1)
|
||||
; CHECK-NEXT: addi r3, r1, -16
|
||||
@ -820,9 +820,9 @@ define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-REG-NEXT: ld r3, -24(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -40(r1)
|
||||
; CHECK-REG-NEXT: add r3, r4, r3
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: std r3, -8(r1)
|
||||
; CHECK-REG-NEXT: ld r3, -32(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: add r3, r4, r3
|
||||
; CHECK-REG-NEXT: std r3, -16(r1)
|
||||
; CHECK-REG-NEXT: addi r3, r1, -16
|
||||
@ -1832,9 +1832,9 @@ define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: lwz r3, -20(r1)
|
||||
; CHECK-NEXT: ld r4, -40(r1)
|
||||
; CHECK-NEXT: sld r3, r4, r3
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: std r3, -8(r1)
|
||||
; CHECK-NEXT: lwz r3, -28(r1)
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: sld r3, r4, r3
|
||||
; CHECK-NEXT: std r3, -16(r1)
|
||||
; CHECK-NEXT: addi r3, r1, -16
|
||||
@ -1850,9 +1850,9 @@ define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-REG-NEXT: lwz r3, -20(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -40(r1)
|
||||
; CHECK-REG-NEXT: sld r3, r4, r3
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: std r3, -8(r1)
|
||||
; CHECK-REG-NEXT: lwz r3, -28(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: sld r3, r4, r3
|
||||
; CHECK-REG-NEXT: std r3, -16(r1)
|
||||
; CHECK-REG-NEXT: addi r3, r1, -16
|
||||
@ -1898,9 +1898,9 @@ define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: lwz r3, -20(r1)
|
||||
; CHECK-NEXT: ld r4, -40(r1)
|
||||
; CHECK-NEXT: srd r3, r4, r3
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: std r3, -8(r1)
|
||||
; CHECK-NEXT: lwz r3, -28(r1)
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: srd r3, r4, r3
|
||||
; CHECK-NEXT: std r3, -16(r1)
|
||||
; CHECK-NEXT: addi r3, r1, -16
|
||||
@ -1916,9 +1916,9 @@ define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-REG-NEXT: lwz r3, -20(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -40(r1)
|
||||
; CHECK-REG-NEXT: srd r3, r4, r3
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: std r3, -8(r1)
|
||||
; CHECK-REG-NEXT: lwz r3, -28(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: srd r3, r4, r3
|
||||
; CHECK-REG-NEXT: std r3, -16(r1)
|
||||
; CHECK-REG-NEXT: addi r3, r1, -16
|
||||
@ -1964,9 +1964,9 @@ define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: lwz r3, -20(r1)
|
||||
; CHECK-NEXT: ld r4, -40(r1)
|
||||
; CHECK-NEXT: srad r3, r4, r3
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: std r3, -8(r1)
|
||||
; CHECK-NEXT: lwz r3, -28(r1)
|
||||
; CHECK-NEXT: ld r4, -48(r1)
|
||||
; CHECK-NEXT: srad r3, r4, r3
|
||||
; CHECK-NEXT: std r3, -16(r1)
|
||||
; CHECK-NEXT: addi r3, r1, -16
|
||||
@ -1982,9 +1982,9 @@ define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-REG-NEXT: lwz r3, -20(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -40(r1)
|
||||
; CHECK-REG-NEXT: srad r3, r4, r3
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: std r3, -8(r1)
|
||||
; CHECK-REG-NEXT: lwz r3, -28(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -48(r1)
|
||||
; CHECK-REG-NEXT: srad r3, r4, r3
|
||||
; CHECK-REG-NEXT: std r3, -16(r1)
|
||||
; CHECK-REG-NEXT: addi r3, r1, -16
|
||||
@ -2148,13 +2148,13 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: stxvd2x v2, 0, r4
|
||||
; CHECK-NEXT: ld r3, -24(r1)
|
||||
; CHECK-NEXT: ld r4, -40(r1)
|
||||
; CHECK-NEXT: ld r6, -48(r1)
|
||||
; CHECK-NEXT: cmpld r4, r3
|
||||
; CHECK-NEXT: li r3, 0
|
||||
; CHECK-NEXT: li r4, -1
|
||||
; CHECK-NEXT: isel r5, r4, r3, lt
|
||||
; CHECK-NEXT: std r5, -8(r1)
|
||||
; CHECK-NEXT: ld r5, -32(r1)
|
||||
; CHECK-NEXT: ld r6, -48(r1)
|
||||
; CHECK-NEXT: cmpld r6, r5
|
||||
; CHECK-NEXT: isel r3, r4, r3, lt
|
||||
; CHECK-NEXT: std r3, -16(r1)
|
||||
@ -2170,13 +2170,13 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-REG-NEXT: stxvd2x v2, 0, r4
|
||||
; CHECK-REG-NEXT: ld r3, -24(r1)
|
||||
; CHECK-REG-NEXT: ld r4, -40(r1)
|
||||
; CHECK-REG-NEXT: ld r6, -48(r1)
|
||||
; CHECK-REG-NEXT: cmpld r4, r3
|
||||
; CHECK-REG-NEXT: li r3, 0
|
||||
; CHECK-REG-NEXT: li r4, -1
|
||||
; CHECK-REG-NEXT: isel r5, r4, r3, lt
|
||||
; CHECK-REG-NEXT: std r5, -8(r1)
|
||||
; CHECK-REG-NEXT: ld r5, -32(r1)
|
||||
; CHECK-REG-NEXT: ld r6, -48(r1)
|
||||
; CHECK-REG-NEXT: cmpld r6, r5
|
||||
; CHECK-REG-NEXT: isel r3, r4, r3, lt
|
||||
; CHECK-REG-NEXT: std r3, -16(r1)
|
||||
|
||||
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Reference in New Issue
Block a user