RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Code Issues Projects Releases Wiki Activity

Specify the value type for the register, not just the size.

Browse Source 
llvm-svn: 7357
This commit is contained in:
Chris Lattner 2003-07-28 04:25:36 +00:00
parent 163559e702
commit da51c38e57
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/Sparc/SparcV9_Reg.td
View File

@ -9,7 +9,10 @@
class V9Reg : Register { set Namespace = "SparcV9"; }
// Ri - One of the 32 64 bit integer registers
class Ri<bits<5> num> : V9Reg { set Size = 64; field bits<5> Num = num; }
class Ri<bits<5> num> : V9Reg {
set RegType = i64; // All integer registers are 64 bits in size
field bits<5> Num = num; // Numbers are identified with a 5 bit ID
}
def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;