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[SystemZ] Introducing assembler dialects for the Z backend
- This patch introduces a different assembler dialect ("hlasm") for z/OS. The default dialect has now been given the "att" dialect name. For this appropriate changes have been added to SystemZ.td. - This patch also makes a few changes to SystemZInstrFormats.td which restrict a few condition code mnemonics to just the "att" dialect variant (he, le, lh, nhe, nle, nlh). These extended condition code mnemonics are not available in HLASM. - A new private function has been introduced in SystemZAsmParser.cpp to return the assembler dialect set in SystemZMCAsmInfo.cpp. The reason we couldn't/haven't explicitly queried the overriden getAssemblerDialect function from AsmParser is outlined in this thread here. This returned dialect is directly passed onto the relevant matcher functions which taken in a variantID, so that the matcher functions can appropriately choose an instruction based on the variant. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D94250
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@ -12,6 +12,7 @@
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInst.h"
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@ -428,6 +429,27 @@ private:
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bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
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bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
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// Both the hlasm and att variants still rely on the basic gnu asm
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// format with respect to inputs, clobbers, outputs etc.
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//
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// However, calling the overriden getAssemblerDialect() method in
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// AsmParser is problematic. It either returns the AssemblerDialect field
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// in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
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// unset, otherwise it returns the private AssemblerDialect field in
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// AsmParser.
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//
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// The problematic part is because, we forcibly set the inline asm dialect
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// in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
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// to the overriden getAssemblerDialect function in AsmParser.cpp, will
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// not return the assembler dialect set in the respective MCAsmInfo instance.
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//
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// For this purpose, we explicitly query the SystemZMCAsmInfo instance
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// here, to get the "correct" assembler dialect, and use it in various
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// functions.
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unsigned getMAIAssemblerDialect() {
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return Parser.getContext().getAsmInfo()->getAssemblerDialect();
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}
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public:
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public:
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SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
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SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
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const MCInstrInfo &MII,
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const MCInstrInfo &MII,
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@ -1325,7 +1347,7 @@ bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
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// Apply mnemonic aliases first, before doing anything else, in
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// Apply mnemonic aliases first, before doing anything else, in
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// case the target uses it.
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// case the target uses it.
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applyMnemonicAliases(Name, getAvailableFeatures(), 0 /*VariantID*/);
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applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
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Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
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Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
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@ -1428,9 +1450,11 @@ bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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MCInst Inst;
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MCInst Inst;
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unsigned MatchResult;
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unsigned MatchResult;
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unsigned Dialect = getMAIAssemblerDialect();
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FeatureBitset MissingFeatures;
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FeatureBitset MissingFeatures;
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MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
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MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
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MissingFeatures, MatchingInlineAsm);
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MatchingInlineAsm, Dialect);
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switch (MatchResult) {
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switch (MatchResult) {
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case Match_Success:
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case Match_Success:
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Inst.setLoc(IDLoc);
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Inst.setLoc(IDLoc);
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@ -1467,7 +1491,7 @@ bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_MnemonicFail: {
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case Match_MnemonicFail: {
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FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
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FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
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std::string Suggestion = SystemZMnemonicSpellCheck(
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std::string Suggestion = SystemZMnemonicSpellCheck(
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((SystemZOperand &)*Operands[0]).getToken(), FBS);
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((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
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return Error(IDLoc, "invalid instruction" + Suggestion,
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return Error(IDLoc, "invalid instruction" + Suggestion,
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((SystemZOperand &)*Operands[0]).getLocRange());
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((SystemZOperand &)*Operands[0]).getLocRange());
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}
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}
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@ -12,11 +12,15 @@
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using namespace llvm;
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using namespace llvm;
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enum AsmDialect { AD_ATT = 0, AD_HLASM = 1 };
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SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
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SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
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CodePointerSize = 8;
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CodePointerSize = 8;
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CalleeSaveStackSlotSize = 8;
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CalleeSaveStackSlotSize = 8;
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IsLittleEndian = false;
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IsLittleEndian = false;
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AssemblerDialect = TT.isOSzOS() ? AD_HLASM : AD_ATT;
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MaxInstLength = 6;
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MaxInstLength = 6;
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CommentString = "#";
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CommentString = "#";
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@ -67,6 +67,20 @@ def SystemZAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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let ShouldEmitMatchRegisterName = 0;
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}
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}
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def ATTAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Variant name.
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string Name = "att";
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}
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def HLASMAsmParserVariant : AsmParserVariant {
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int Variant = 1;
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// Variant name.
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string Name = "hlasm";
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Top-level target declaration
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// Top-level target declaration
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -74,5 +88,6 @@ def SystemZAsmParser : AsmParser {
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def SystemZ : Target {
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def SystemZ : Target {
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let InstructionSet = SystemZInstrInfo;
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let InstructionSet = SystemZInstrInfo;
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let AssemblyParsers = [SystemZAsmParser];
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let AssemblyParsers = [SystemZAsmParser];
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let AssemblyParserVariants = [ATTAsmParserVariant, HLASMAsmParserVariant];
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let AllowRegisterRenaming = 1;
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let AllowRegisterRenaming = 1;
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}
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}
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@ -1845,7 +1845,8 @@ class DirectiveInsnVSI<dag outs, dag ins, string asmstr, list<dag> pattern>
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// A class to describe a variant of an instruction with condition mask.
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// A class to describe a variant of an instruction with condition mask.
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class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
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class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein,
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string asmvariantin = ""> {
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// The fixed condition mask to use.
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// The fixed condition mask to use.
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bits<4> ccmask = ccmaskin;
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bits<4> ccmask = ccmaskin;
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@ -1854,6 +1855,11 @@ class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
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// Whether this is an alternate that needs to be marked isAsmParserOnly.
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// Whether this is an alternate that needs to be marked isAsmParserOnly.
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bit alternate = alternatein;
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bit alternate = alternatein;
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// Whether this needs be to restricted to a specific dialect.
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// Valid values are "att" and "hlasm", which when passed in
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// will set AsmVariantName.
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string asmvariant = asmvariantin;
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}
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}
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// Condition mask 15 means "always true", which is used to define
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// Condition mask 15 means "always true", which is used to define
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@ -1864,20 +1870,20 @@ def CondAlways : CondVariant<15, "", 0>;
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def CondVariantO : CondVariant<1, "o", 0>;
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def CondVariantO : CondVariant<1, "o", 0>;
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def CondVariantH : CondVariant<2, "h", 0>;
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def CondVariantH : CondVariant<2, "h", 0>;
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def CondVariantP : CondVariant<2, "p", 1>;
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def CondVariantP : CondVariant<2, "p", 1>;
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def CondVariantNLE : CondVariant<3, "nle", 0>;
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def CondVariantNLE : CondVariant<3, "nle", 0, "att">;
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def CondVariantL : CondVariant<4, "l", 0>;
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def CondVariantL : CondVariant<4, "l", 0>;
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def CondVariantM : CondVariant<4, "m", 1>;
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def CondVariantM : CondVariant<4, "m", 1>;
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def CondVariantNHE : CondVariant<5, "nhe", 0>;
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def CondVariantNHE : CondVariant<5, "nhe", 0, "att">;
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def CondVariantLH : CondVariant<6, "lh", 0>;
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def CondVariantLH : CondVariant<6, "lh", 0, "att">;
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def CondVariantNE : CondVariant<7, "ne", 0>;
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def CondVariantNE : CondVariant<7, "ne", 0>;
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def CondVariantNZ : CondVariant<7, "nz", 1>;
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def CondVariantNZ : CondVariant<7, "nz", 1>;
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def CondVariantE : CondVariant<8, "e", 0>;
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def CondVariantE : CondVariant<8, "e", 0>;
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def CondVariantZ : CondVariant<8, "z", 1>;
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def CondVariantZ : CondVariant<8, "z", 1>;
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def CondVariantNLH : CondVariant<9, "nlh", 0>;
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def CondVariantNLH : CondVariant<9, "nlh", 0, "att">;
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def CondVariantHE : CondVariant<10, "he", 0>;
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def CondVariantHE : CondVariant<10, "he", 0, "att">;
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def CondVariantNL : CondVariant<11, "nl", 0>;
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def CondVariantNL : CondVariant<11, "nl", 0>;
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def CondVariantNM : CondVariant<11, "nm", 1>;
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def CondVariantNM : CondVariant<11, "nm", 1>;
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def CondVariantLE : CondVariant<12, "le", 0>;
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def CondVariantLE : CondVariant<12, "le", 0, "att">;
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def CondVariantNH : CondVariant<13, "nh", 0>;
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def CondVariantNH : CondVariant<13, "nh", 0>;
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def CondVariantNP : CondVariant<13, "np", 1>;
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def CondVariantNP : CondVariant<13, "np", 1>;
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def CondVariantNO : CondVariant<14, "no", 0>;
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def CondVariantNO : CondVariant<14, "no", 0>;
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@ -1886,35 +1892,38 @@ def CondVariantNO : CondVariant<14, "no", 0>;
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class CV<string name>
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class CV<string name>
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: CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
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: CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
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!cast<CondVariant>("CondVariant"#name).suffix,
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!cast<CondVariant>("CondVariant"#name).suffix,
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!cast<CondVariant>("CondVariant"#name).alternate>;
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!cast<CondVariant>("CondVariant"#name).alternate,
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!cast<CondVariant>("CondVariant"#name).asmvariant>;
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// Condition masks for integer instructions (e.g. compare-and-branch).
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// Condition masks for integer instructions (e.g. compare-and-branch).
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// This is like the list above, except that condition 3 is not possible
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// This is like the list above, except that condition 3 is not possible
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// and that the low bit of the mask is therefore always 0. This means
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// and that the low bit of the mask is therefore always 0. This means
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// that each condition has two names. Conditions "o" and "no" are not used.
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// that each condition has two names. Conditions "o" and "no" are not used.
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def IntCondVariantH : CondVariant<2, "h", 0>;
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def IntCondVariantH : CondVariant<2, "h", 0>;
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def IntCondVariantNLE : CondVariant<2, "nle", 1>;
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def IntCondVariantNLE : CondVariant<2, "nle", 1, "att">;
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def IntCondVariantL : CondVariant<4, "l", 0>;
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def IntCondVariantL : CondVariant<4, "l", 0>;
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def IntCondVariantNHE : CondVariant<4, "nhe", 1>;
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def IntCondVariantNHE : CondVariant<4, "nhe", 1, "att">;
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def IntCondVariantLH : CondVariant<6, "lh", 0>;
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def IntCondVariantLH : CondVariant<6, "lh", 0, "att">;
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def IntCondVariantNE : CondVariant<6, "ne", 1>;
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def IntCondVariantNE : CondVariant<6, "ne", 1>;
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def IntCondVariantE : CondVariant<8, "e", 0>;
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def IntCondVariantE : CondVariant<8, "e", 0>;
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def IntCondVariantNLH : CondVariant<8, "nlh", 1>;
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def IntCondVariantNLH : CondVariant<8, "nlh", 1, "att">;
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def IntCondVariantHE : CondVariant<10, "he", 0>;
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def IntCondVariantHE : CondVariant<10, "he", 0, "att">;
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def IntCondVariantNL : CondVariant<10, "nl", 1>;
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def IntCondVariantNL : CondVariant<10, "nl", 1>;
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def IntCondVariantLE : CondVariant<12, "le", 0>;
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def IntCondVariantLE : CondVariant<12, "le", 0, "att">;
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def IntCondVariantNH : CondVariant<12, "nh", 1>;
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def IntCondVariantNH : CondVariant<12, "nh", 1>;
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// A helper class to look up one of the above by name.
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// A helper class to look up one of the above by name.
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class ICV<string name>
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class ICV<string name>
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: CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
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: CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
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!cast<CondVariant>("IntCondVariant"#name).suffix,
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!cast<CondVariant>("IntCondVariant"#name).suffix,
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!cast<CondVariant>("IntCondVariant"#name).alternate>;
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!cast<CondVariant>("IntCondVariant"#name).alternate,
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!cast<CondVariant>("IntCondVariant"#name).asmvariant>;
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// Defines a class that makes it easier to define
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// Defines a class that makes it easier to define
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// a MnemonicAlias when CondVariant's are involved.
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// a MnemonicAlias when CondVariant's are involved.
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class MnemonicCondBranchAlias<CondVariant V, string from, string to>
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class MnemonicCondBranchAlias<CondVariant V, string from, string to>
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: MnemonicAlias<!subst("#", V.suffix, from), !subst("#", V.suffix, to)>;
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: MnemonicAlias<!subst("#", V.suffix, from), !subst("#", V.suffix, to),
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V.asmvariant>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction definitions with semantics
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// Instruction definitions with semantics
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@ -2125,6 +2134,7 @@ class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
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: InstRIc<opcode, (outs), (ins brtarget16:$RI2),
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: InstRIc<opcode, (outs), (ins brtarget16:$RI2),
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!subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
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!subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
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let isAsmParserOnly = V.alternate;
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let isAsmParserOnly = V.alternate;
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let AsmVariantName = V.asmvariant;
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let M1 = V.ccmask;
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let M1 = V.ccmask;
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}
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}
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@ -2142,6 +2152,7 @@ class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
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: InstRILc<opcode, (outs), (ins brtarget32:$RI2),
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: InstRILc<opcode, (outs), (ins brtarget32:$RI2),
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!subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
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!subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
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let isAsmParserOnly = V.alternate;
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let isAsmParserOnly = V.alternate;
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let AsmVariantName = V.asmvariant;
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let M1 = V.ccmask;
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let M1 = V.ccmask;
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}
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}
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@ -2160,6 +2171,7 @@ class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
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: InstRR<opcode, (outs), (ins ADDR64:$R2),
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: InstRR<opcode, (outs), (ins ADDR64:$R2),
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!subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
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!subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
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let isAsmParserOnly = V.alternate;
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let isAsmParserOnly = V.alternate;
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let AsmVariantName = V.asmvariant;
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let R1 = V.ccmask;
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let R1 = V.ccmask;
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}
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}
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@ -2177,6 +2189,7 @@ class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
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: InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
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: InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
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!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
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!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
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let isAsmParserOnly = V.alternate;
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let isAsmParserOnly = V.alternate;
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let AsmVariantName = V.asmvariant;
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let M1 = V.ccmask;
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let M1 = V.ccmask;
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}
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}
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@ -2199,6 +2212,7 @@ class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
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!subst("#", V.suffix, mnemonic)#"\t$XBD2",
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!subst("#", V.suffix, mnemonic)#"\t$XBD2",
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[(operator (load bdxaddr20only:$XBD2))]> {
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[(operator (load bdxaddr20only:$XBD2))]> {
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let isAsmParserOnly = V.alternate;
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let isAsmParserOnly = V.alternate;
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let AsmVariantName = V.asmvariant;
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let M1 = V.ccmask;
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let M1 = V.ccmask;
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let mayLoad = 1;
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let mayLoad = 1;
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}
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}
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@ -2218,6 +2232,7 @@ class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
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: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
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: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
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mnemonic#V.suffix#"\t$R1, $I2", []> {
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mnemonic#V.suffix#"\t$R1, $I2", []> {
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let isAsmParserOnly = V.alternate;
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let isAsmParserOnly = V.alternate;
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let AsmVariantName = V.asmvariant;
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||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2245,6 +2260,7 @@ class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
: InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
|
: InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
|
||||||
mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
|
mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2272,6 +2288,7 @@ class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
: InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
|
: InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
|
||||||
mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
|
mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2304,6 +2321,7 @@ class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
: InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
|
: InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
|
||||||
mnemonic#V.suffix#"\t$R1, $R2", []> {
|
mnemonic#V.suffix#"\t$R1, $R2", []> {
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2324,6 +2342,7 @@ class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
: InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
|
: InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
|
||||||
mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
|
mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2351,6 +2370,7 @@ class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
: InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
|
: InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
|
||||||
mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
|
mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2383,6 +2403,7 @@ class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
: InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
|
: InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
|
||||||
mnemonic#V.suffix#"\t$R1, $BD2", []> {
|
mnemonic#V.suffix#"\t$R1, $BD2", []> {
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2717,6 +2738,7 @@ class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
let mayStore = 1;
|
let mayStore = 1;
|
||||||
let AccessBytes = bytes;
|
let AccessBytes = bytes;
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2891,6 +2913,7 @@ class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
let mayLoad = 1;
|
let mayLoad = 1;
|
||||||
let AccessBytes = bytes;
|
let AccessBytes = bytes;
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -3294,6 +3317,7 @@ class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
let Constraints = "$R1 = $R1src";
|
let Constraints = "$R1 = $R1src";
|
||||||
let DisableEncoding = "$R1src";
|
let DisableEncoding = "$R1src";
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -3332,6 +3356,7 @@ class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
: InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
|
: InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
|
||||||
mnemonic#V.suffix#"\t$R1, $R2, $R3", []> {
|
mnemonic#V.suffix#"\t$R1, $R2, $R3", []> {
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M4 = V.ccmask;
|
let M4 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -3401,6 +3426,7 @@ class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
|
|||||||
let Constraints = "$R1 = $R1src";
|
let Constraints = "$R1 = $R1src";
|
||||||
let DisableEncoding = "$R1src";
|
let DisableEncoding = "$R1src";
|
||||||
let isAsmParserOnly = V.alternate;
|
let isAsmParserOnly = V.alternate;
|
||||||
|
let AsmVariantName = V.asmvariant;
|
||||||
let M3 = V.ccmask;
|
let M3 = V.ccmask;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user