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[PowerPC] Handle inline assembly clobber of link regsiter
This patch adds the handling of clobbers of the link register LR for inline assembly. This patch is to fix: https://bugs.llvm.org/show_bug.cgi?id=50147 Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D101657
This commit is contained in:
Stefan Pintilie
parent
f285520094
commit
da8040707c
@ -166,6 +166,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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// Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
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// Custom lower inline assembly to check for special registers.
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setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
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setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
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// PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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@ -3625,6 +3629,57 @@ SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
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return Op.getOperand(0);
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}
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SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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PPCFunctionInfo &MFI = *MF.getInfo<PPCFunctionInfo>();
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assert((Op.getOpcode() == ISD::INLINEASM ||
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Op.getOpcode() == ISD::INLINEASM_BR) &&
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"Expecting Inline ASM node.");
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// If an LR store is already known to be required then there is not point in
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// checking this ASM as well.
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if (MFI.isLRStoreRequired())
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return Op;
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// Inline ASM nodes have an optional last operand that is an incoming Flag of
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// type MVT::Glue. We want to ignore this last operand if that is the case.
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unsigned NumOps = Op.getNumOperands();
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if (Op.getOperand(NumOps - 1).getValueType() == MVT::Glue)
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--NumOps;
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// Check all operands that may contain the LR.
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for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
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unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
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unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
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++i; // Skip the ID value.
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switch (InlineAsm::getKind(Flags)) {
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default:
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llvm_unreachable("Bad flags!");
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case InlineAsm::Kind_RegUse:
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case InlineAsm::Kind_Imm:
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case InlineAsm::Kind_Mem:
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i += NumVals;
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break;
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case InlineAsm::Kind_Clobber:
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case InlineAsm::Kind_RegDef:
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case InlineAsm::Kind_RegDefEarlyClobber: {
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for (; NumVals; --NumVals, ++i) {
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Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
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if (Reg != PPC::LR && Reg != PPC::LR8)
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continue;
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MFI.setLRStoreRequired();
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return Op;
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}
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break;
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}
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}
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}
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return Op;
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}
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SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
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SelectionDAG &DAG) const {
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if (Subtarget.isAIXABI())
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@ -10735,6 +10790,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
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case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
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case ISD::INLINEASM:
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case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG);
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// Variable argument lowering.
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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case ISD::VAARG: return LowerVAARG(Op, DAG);
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@ -15583,6 +15640,11 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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return std::make_pair(0U, &PPC::VSSRCRegClass);
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else
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return std::make_pair(0U, &PPC::VSFRCRegClass);
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} else if (Constraint == "lr") {
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if (VT == MVT::i64)
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return std::make_pair(0U, &PPC::LR8RCRegClass);
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else
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return std::make_pair(0U, &PPC::LRRCRegClass);
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}
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// Handle special cases of physical registers that are not properly handled
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@ -1197,6 +1197,7 @@ namespace llvm {
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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@ -409,6 +409,13 @@ def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
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let isAllocatable = 0;
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}
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def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> {
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let isAllocatable = 0;
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}
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def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {
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let isAllocatable = 0;
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}
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def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
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def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
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let CopyCost = -1;
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264
test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
Normal file
264
test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
Normal file
@ -0,0 +1,264 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-unknown -verify-machineinstrs %s \
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; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64LE
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; RUN: llc -mtriple=powerpc64-unknown-linux-unknown -verify-machineinstrs %s \
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; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64BE
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define dso_local void @ClobberLR() local_unnamed_addr #0 {
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; PPC64LE-LABEL: ClobberLR:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: mflr r0
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; PPC64LE-NEXT: std r0, 16(r1)
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; PPC64LE-NEXT: stdu r1, -32(r1)
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: addi r1, r1, 32
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; PPC64LE-NEXT: ld r0, 16(r1)
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; PPC64LE-NEXT: mtlr r0
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: ClobberLR:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: mflr r0
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; PPC64BE-NEXT: std r0, 16(r1)
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; PPC64BE-NEXT: stdu r1, -48(r1)
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: addi r1, r1, 48
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; PPC64BE-NEXT: ld r0, 16(r1)
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; PPC64BE-NEXT: mtlr r0
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; PPC64BE-NEXT: blr
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entry:
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tail call void asm sideeffect "", "~{lr}"()
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ret void
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}
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define dso_local void @ClobberR5() local_unnamed_addr #0 {
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; PPC64LE-LABEL: ClobberR5:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: ClobberR5:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: blr
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entry:
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tail call void asm sideeffect "", "~{r5}"()
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ret void
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}
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define dso_local void @ClobberR15() local_unnamed_addr #0 {
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; PPC64LE-LABEL: ClobberR15:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: std r15, -136(r1) # 8-byte Folded Spill
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: ClobberR15:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: std r15, -136(r1) # 8-byte Folded Spill
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
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; PPC64BE-NEXT: blr
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entry:
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tail call void asm sideeffect "", "~{r15}"()
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ret void
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}
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;; Test for INLINEASM_BR
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define dso_local signext i32 @ClobberLR_BR(i32 signext %in) #0 {
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; PPC64LE-LABEL: ClobberLR_BR:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: nop
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: # %bb.1: # %return
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; PPC64LE-NEXT: extsw r3, r3
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; PPC64LE-NEXT: blr
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; PPC64LE-NEXT: .Ltmp0: # Block address taken
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; PPC64LE-NEXT: .LBB3_2: # %return_early
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; PPC64LE-NEXT: mflr r0
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; PPC64LE-NEXT: std r0, 16(r1)
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; PPC64LE-NEXT: stdu r1, -32(r1)
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; PPC64LE-NEXT: li r3, 0
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; PPC64LE-NEXT: addi r1, r1, 32
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; PPC64LE-NEXT: ld r0, 16(r1)
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; PPC64LE-NEXT: mtlr r0
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; PPC64LE-NEXT: extsw r3, r3
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: ClobberLR_BR:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: nop
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: # %bb.1: # %return
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; PPC64BE-NEXT: extsw r3, r3
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; PPC64BE-NEXT: blr
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; PPC64BE-NEXT: .Ltmp0: # Block address taken
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; PPC64BE-NEXT: .LBB3_2: # %return_early
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; PPC64BE-NEXT: mflr r0
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; PPC64BE-NEXT: std r0, 16(r1)
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; PPC64BE-NEXT: stdu r1, -48(r1)
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; PPC64BE-NEXT: li r3, 0
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; PPC64BE-NEXT: addi r1, r1, 48
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; PPC64BE-NEXT: ld r0, 16(r1)
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; PPC64BE-NEXT: mtlr r0
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; PPC64BE-NEXT: extsw r3, r3
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; PPC64BE-NEXT: blr
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entry:
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callbr void asm sideeffect "nop", "X,~{lr}"(i8* blockaddress(@ClobberLR_BR, %return_early))
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to label %return [label %return_early]
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return_early:
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br label %return
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return:
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%retval.0 = phi i32 [ 0, %return_early ], [ %in, %entry ]
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ret i32 %retval.0
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}
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define dso_local signext i32 @ClobberR5_BR(i32 signext %in) #0 {
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; PPC64LE-LABEL: ClobberR5_BR:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: nop
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: # %bb.1: # %return
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; PPC64LE-NEXT: extsw r3, r3
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; PPC64LE-NEXT: blr
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; PPC64LE-NEXT: .Ltmp1: # Block address taken
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; PPC64LE-NEXT: .LBB4_2: # %return_early
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; PPC64LE-NEXT: li r3, 0
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; PPC64LE-NEXT: extsw r3, r3
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: ClobberR5_BR:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: nop
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: # %bb.1: # %return
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; PPC64BE-NEXT: extsw r3, r3
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; PPC64BE-NEXT: blr
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; PPC64BE-NEXT: .Ltmp1: # Block address taken
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; PPC64BE-NEXT: .LBB4_2: # %return_early
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; PPC64BE-NEXT: li r3, 0
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; PPC64BE-NEXT: extsw r3, r3
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; PPC64BE-NEXT: blr
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entry:
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callbr void asm sideeffect "nop", "X,~{r5}"(i8* blockaddress(@ClobberR5_BR, %return_early))
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to label %return [label %return_early]
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return_early:
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br label %return
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return:
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%retval.0 = phi i32 [ 0, %return_early ], [ %in, %entry ]
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ret i32 %retval.0
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}
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define dso_local void @DefLR() local_unnamed_addr #0 {
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; PPC64LE-LABEL: DefLR:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: mflr r0
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; PPC64LE-NEXT: std r0, 16(r1)
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; PPC64LE-NEXT: stdu r1, -32(r1)
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: addi r1, r1, 32
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; PPC64LE-NEXT: ld r0, 16(r1)
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; PPC64LE-NEXT: mtlr r0
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: DefLR:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: mflr r0
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; PPC64BE-NEXT: std r0, 16(r1)
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; PPC64BE-NEXT: stdu r1, -48(r1)
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: addi r1, r1, 48
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; PPC64BE-NEXT: ld r0, 16(r1)
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; PPC64BE-NEXT: mtlr r0
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; PPC64BE-NEXT: blr
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entry:
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tail call i64 asm sideeffect "", "={lr}"()
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ret void
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}
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define dso_local void @EarlyClobberLR() local_unnamed_addr #0 {
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; PPC64LE-LABEL: EarlyClobberLR:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: mflr r0
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; PPC64LE-NEXT: std r0, 16(r1)
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; PPC64LE-NEXT: stdu r1, -32(r1)
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: addi r1, r1, 32
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; PPC64LE-NEXT: ld r0, 16(r1)
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; PPC64LE-NEXT: mtlr r0
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: EarlyClobberLR:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: mflr r0
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; PPC64BE-NEXT: std r0, 16(r1)
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; PPC64BE-NEXT: stdu r1, -48(r1)
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: addi r1, r1, 48
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; PPC64BE-NEXT: ld r0, 16(r1)
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; PPC64BE-NEXT: mtlr r0
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; PPC64BE-NEXT: blr
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entry:
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tail call i64 asm sideeffect "", "=&{lr}"()
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ret void
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}
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define dso_local void @ClobberMulti() local_unnamed_addr #0 {
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; PPC64LE-LABEL: ClobberMulti:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: mflr r0
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; PPC64LE-NEXT: std r15, -136(r1) # 8-byte Folded Spill
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; PPC64LE-NEXT: std r16, -128(r1) # 8-byte Folded Spill
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; PPC64LE-NEXT: std r0, 16(r1)
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; PPC64LE-NEXT: stdu r1, -176(r1)
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; PPC64LE-NEXT: #APP
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; PPC64LE-NEXT: #NO_APP
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; PPC64LE-NEXT: addi r1, r1, 176
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; PPC64LE-NEXT: ld r0, 16(r1)
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; PPC64LE-NEXT: ld r16, -128(r1) # 8-byte Folded Reload
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; PPC64LE-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
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; PPC64LE-NEXT: mtlr r0
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; PPC64LE-NEXT: blr
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;
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; PPC64BE-LABEL: ClobberMulti:
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; PPC64BE: # %bb.0: # %entry
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; PPC64BE-NEXT: mflr r0
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; PPC64BE-NEXT: std r0, 16(r1)
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; PPC64BE-NEXT: stdu r1, -192(r1)
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; PPC64BE-NEXT: std r15, 56(r1) # 8-byte Folded Spill
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; PPC64BE-NEXT: std r16, 64(r1) # 8-byte Folded Spill
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; PPC64BE-NEXT: #APP
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; PPC64BE-NEXT: #NO_APP
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; PPC64BE-NEXT: ld r16, 64(r1) # 8-byte Folded Reload
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; PPC64BE-NEXT: ld r15, 56(r1) # 8-byte Folded Reload
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; PPC64BE-NEXT: addi r1, r1, 192
|
||||
; PPC64BE-NEXT: ld r0, 16(r1)
|
||||
; PPC64BE-NEXT: mtlr r0
|
||||
; PPC64BE-NEXT: blr
|
||||
entry:
|
||||
tail call void asm sideeffect "", "~{lr},~{r15},~{r16}"()
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
Loading…
Reference in New Issue
Block a user