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[Hexagon] Fix fshl/fshr -> combine() bug identified in D75114
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@ -1095,7 +1095,7 @@ def Divu64_8: SDNodeXForm<imm, [{
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// Special cases:
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let AddedComplexity = 100 in {
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def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)),
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(A2_combine_hl I32:$Rs, I32:$Rt)>;
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(A2_combine_lh I32:$Rs, I32:$Rt)>;
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def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S),
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(S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>;
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}
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@ -1129,7 +1129,7 @@ def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru),
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// Special cases:
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let AddedComplexity = 100 in {
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def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)),
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(A2_combine_hl I32:$Rs, I32:$Rt)>;
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(A2_combine_lh I32:$Rs, I32:$Rt)>;
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def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S),
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(S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>;
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}
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@ -257,7 +257,7 @@ b0:
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}
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; CHECK-LABEL: f30:
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; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
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; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
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define i32 @f30(i32 %a0, i32 %a1) #1 {
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b0:
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%v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 16)
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@ -265,7 +265,7 @@ b0:
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}
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; CHECK-LABEL: f31:
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; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
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; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
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define i32 @f31(i32 %a0, i32 %a1) #1 {
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b0:
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%v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 16)
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