mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
Cleaned up code layout. No functional changes.
llvm-svn: 6304
This commit is contained in:
Misha Brukman
parent
1cab8ed666
commit
daf2cc3c48
File diff suppressed because it is too large
Load Diff
@ -249,20 +249,21 @@ SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
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// Delete and disconnect all in-edges for the node
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for (SchedGraphNode::iterator I = node->beginInEdges();
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I != node->endInEdges(); ++I)
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{
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SchedGraphNode* srcNode = (*I)->getSrc();
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srcNode->removeOutEdge(*I);
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delete *I;
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{
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SchedGraphNode* srcNode = (*I)->getSrc();
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srcNode->removeOutEdge(*I);
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delete *I;
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if (addDummyEdges &&
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srcNode != getRoot() &&
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srcNode->beginOutEdges() == srcNode->endOutEdges())
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{ // srcNode has no more out edges, so add an edge to dummy EXIT node
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assert(node != getLeaf() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(srcNode, getLeaf(),
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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if (addDummyEdges &&
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srcNode != getRoot() &&
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srcNode->beginOutEdges() == srcNode->endOutEdges())
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{
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// srcNode has no more out edges, so add an edge to dummy EXIT node
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assert(node != getLeaf() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(srcNode, getLeaf(),
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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}
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node->inEdges.clear();
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}
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@ -273,20 +274,20 @@ SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
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// Delete and disconnect all out-edges for the node
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for (SchedGraphNode::iterator I = node->beginOutEdges();
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I != node->endOutEdges(); ++I)
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{
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SchedGraphNode* sinkNode = (*I)->getSink();
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sinkNode->removeInEdge(*I);
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delete *I;
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{
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SchedGraphNode* sinkNode = (*I)->getSink();
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sinkNode->removeInEdge(*I);
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delete *I;
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if (addDummyEdges &&
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sinkNode != getLeaf() &&
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sinkNode->beginInEdges() == sinkNode->endInEdges())
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{ //sinkNode has no more in edges, so add an edge from dummy ENTRY node
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assert(node != getRoot() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(getRoot(), sinkNode,
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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if (addDummyEdges &&
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sinkNode != getLeaf() &&
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sinkNode->beginInEdges() == sinkNode->endInEdges())
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{ //sinkNode has no more in edges, so add an edge from dummy ENTRY node
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assert(node != getRoot() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(getRoot(), sinkNode,
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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}
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node->outEdges.clear();
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}
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@ -305,16 +306,16 @@ SchedGraph::addDummyEdges()
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assert(graphRoot->outEdges.size() == 0);
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for (const_iterator I=begin(); I != end(); ++I)
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{
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SchedGraphNode* node = (*I).second;
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assert(node != graphRoot && node != graphLeaf);
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if (node->beginInEdges() == node->endInEdges())
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(void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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if (node->beginOutEdges() == node->endOutEdges())
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(void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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{
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SchedGraphNode* node = (*I).second;
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assert(node != graphRoot && node != graphLeaf);
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if (node->beginInEdges() == node->endInEdges())
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(void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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if (node->beginOutEdges() == node->endOutEdges())
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(void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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@ -343,65 +344,65 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
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// Use a latency of 0 because we only need to prevent out-of-order issue.
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//
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for (unsigned i = termMvec.size(); i > first+1; --i)
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{
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SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
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assert(toNode && "No node for instr generated for branch/ret?");
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{
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SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
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assert(toNode && "No node for instr generated for branch/ret?");
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for (unsigned j = i-1; j != 0; --j)
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if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
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mii.isReturn(termMvec[j-1]->getOpCode()))
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{
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SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
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assert(brNode && "No node for instr generated for branch/ret?");
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(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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break; // only one incoming edge is enough
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}
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}
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for (unsigned j = i-1; j != 0; --j)
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if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
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mii.isReturn(termMvec[j-1]->getOpCode()))
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{
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SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
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assert(brNode && "No node for instr generated for branch/ret?");
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(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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break; // only one incoming edge is enough
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}
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}
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// Add CD edges from each instruction preceding the first branch
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// to the first branch. Use a latency of 0 as above.
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//
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for (unsigned i = first; i != 0; --i)
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{
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SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
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assert(fromNode && "No node for instr generated for branch?");
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(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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{
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SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
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assert(fromNode && "No node for instr generated for branch?");
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(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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for (unsigned i=0, N=MBB.size(); i < N; i++)
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{
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if (MBB[i] == termMvec[first]) // reached the first branch
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break;
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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if (MBB[i] == termMvec[first]) // reached the first branch
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break;
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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}
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}
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static const int SG_LOAD_REF = 0;
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@ -437,24 +438,24 @@ SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
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// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
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//
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for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
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{
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MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
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int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
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: mii.isLoad(fromOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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for (unsigned jm=im+1; jm < NM; jm++)
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{
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MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
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int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
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: mii.isLoad(fromOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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for (unsigned jm=im+1; jm < NM; jm++)
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{
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MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
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int toType = mii.isCall(toOpCode)? SG_CALL_REF
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: mii.isLoad(toOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
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int toType = mii.isCall(toOpCode)? SG_CALL_REF
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: mii.isLoad(toOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
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(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
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SchedGraphEdge::MemoryDep,
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SG_DepOrderArray[fromType][toType], 1);
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}
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if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
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(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
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SchedGraphEdge::MemoryDep,
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SG_DepOrderArray[fromType][toType], 1);
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}
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}
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}
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// Add edges from/to CC reg instrs to/from call instrs.
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@ -484,24 +485,23 @@ SchedGraph::addCallCCEdges(const std::vector<SchedGraphNode*>& memNodeVec,
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int lastCallNodeIdx = -1;
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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if (mii.isCall(bbMvec[i]->getOpCode()))
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{
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++lastCallNodeIdx;
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for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
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if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
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break;
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assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
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}
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else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
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{ // Add incoming/outgoing edges from/to preceding/later calls
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SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
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int j=0;
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for ( ; j <= lastCallNodeIdx; j++)
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(void) new SchedGraphEdge(callNodeVec[j], ccNode,
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MachineCCRegsRID, 0);
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for ( ; j < (int) callNodeVec.size(); j++)
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(void) new SchedGraphEdge(ccNode, callNodeVec[j],
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MachineCCRegsRID, 0);
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}
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{
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++lastCallNodeIdx;
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for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
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if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
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break;
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assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
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} else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
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// Add incoming/outgoing edges from/to preceding/later calls
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SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
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int j=0;
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for ( ; j <= lastCallNodeIdx; j++)
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(void) new SchedGraphEdge(callNodeVec[j], ccNode,
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MachineCCRegsRID, 0);
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for ( ; j < (int) callNodeVec.size(); j++)
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(void) new SchedGraphEdge(ccNode, callNodeVec[j],
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MachineCCRegsRID, 0);
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}
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}
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@ -517,47 +517,43 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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//
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for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
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I != regToRefVecMap.end(); ++I)
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{
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int regNum = (*I).first;
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RefVec& regRefVec = (*I).second;
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{
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int regNum = (*I).first;
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RefVec& regRefVec = (*I).second;
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// regRefVec is ordered by control flow order in the basic block
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for (unsigned i=0; i < regRefVec.size(); ++i)
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{
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SchedGraphNode* node = regRefVec[i].first;
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unsigned int opNum = regRefVec[i].second;
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bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
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bool isDefAndUse =
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node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
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// regRefVec is ordered by control flow order in the basic block
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for (unsigned i=0; i < regRefVec.size(); ++i) {
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SchedGraphNode* node = regRefVec[i].first;
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unsigned int opNum = regRefVec[i].second;
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bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
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bool isDefAndUse =
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node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
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for (unsigned p=0; p < i; ++p)
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{
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SchedGraphNode* prevNode = regRefVec[p].first;
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if (prevNode != node)
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{
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unsigned int prevOpNum = regRefVec[p].second;
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bool prevIsDef =
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prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
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bool prevIsDefAndUse =
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prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
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if (isDef)
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{
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if (prevIsDef)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::OutputDep);
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if (!prevIsDef || prevIsDefAndUse)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::AntiDep);
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}
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for (unsigned p=0; p < i; ++p) {
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SchedGraphNode* prevNode = regRefVec[p].first;
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if (prevNode != node) {
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unsigned int prevOpNum = regRefVec[p].second;
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bool prevIsDef =
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prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
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bool prevIsDefAndUse =
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prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
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if (isDef) {
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if (prevIsDef)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::OutputDep);
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if (!prevIsDef || prevIsDefAndUse)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::AntiDep);
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}
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if (prevIsDef)
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if (!isDef || isDefAndUse)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::TrueDep);
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}
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}
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if (prevIsDef)
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if (!isDef || isDefAndUse)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::TrueDep);
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}
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}
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}
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}
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}
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@ -578,29 +574,28 @@ SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
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// Add true or output dep edges from all def nodes before refNode in BB.
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// Add anti or output dep edges to all def nodes after refNode.
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for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
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{
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if ((*I).first == refNode)
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continue; // Dont add any self-loops
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{
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if ((*I).first == refNode)
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continue; // Dont add any self-loops
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if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
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{ // (*).first is before refNode
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if (refNodeIsDef)
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(void) new SchedGraphEdge((*I).first, refNode, defValue,
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SchedGraphEdge::OutputDep);
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if (refNodeIsUse)
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(void) new SchedGraphEdge((*I).first, refNode, defValue,
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SchedGraphEdge::TrueDep);
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}
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else
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{ // (*).first is after refNode
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if (refNodeIsDef)
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(void) new SchedGraphEdge(refNode, (*I).first, defValue,
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SchedGraphEdge::OutputDep);
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if (refNodeIsUse)
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(void) new SchedGraphEdge(refNode, (*I).first, defValue,
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SchedGraphEdge::AntiDep);
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}
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if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
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// (*).first is before refNode
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if (refNodeIsDef)
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(void) new SchedGraphEdge((*I).first, refNode, defValue,
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SchedGraphEdge::OutputDep);
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if (refNodeIsUse)
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(void) new SchedGraphEdge((*I).first, refNode, defValue,
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SchedGraphEdge::TrueDep);
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} else {
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// (*).first is after refNode
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if (refNodeIsDef)
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(void) new SchedGraphEdge(refNode, (*I).first, defValue,
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SchedGraphEdge::OutputDep);
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if (refNodeIsUse)
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(void) new SchedGraphEdge(refNode, (*I).first, defValue,
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SchedGraphEdge::AntiDep);
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}
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}
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}
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@ -616,35 +611,35 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
|
||||
// Add edges for all operands of the machine instruction.
|
||||
//
|
||||
for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
|
||||
{
|
||||
switch (MI.getOperandType(i))
|
||||
{
|
||||
switch (MI.getOperandType(i))
|
||||
{
|
||||
case MachineOperand::MO_VirtualRegister:
|
||||
case MachineOperand::MO_CCRegister:
|
||||
if (const Instruction* srcI =
|
||||
dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
|
||||
{
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addEdgesForValue(node, I->second, srcI,
|
||||
MI.operandIsDefined(i),
|
||||
MI.operandIsDefinedAndUsed(i), target);
|
||||
}
|
||||
break;
|
||||
case MachineOperand::MO_VirtualRegister:
|
||||
case MachineOperand::MO_CCRegister:
|
||||
if (const Instruction* srcI =
|
||||
dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
|
||||
{
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addEdgesForValue(node, I->second, srcI,
|
||||
MI.operandIsDefined(i),
|
||||
MI.operandIsDefinedAndUsed(i), target);
|
||||
}
|
||||
break;
|
||||
|
||||
case MachineOperand::MO_MachineRegister:
|
||||
break;
|
||||
case MachineOperand::MO_MachineRegister:
|
||||
break;
|
||||
|
||||
case MachineOperand::MO_SignExtendedImmed:
|
||||
case MachineOperand::MO_UnextendedImmed:
|
||||
case MachineOperand::MO_PCRelativeDisp:
|
||||
break; // nothing to do for immediate fields
|
||||
case MachineOperand::MO_SignExtendedImmed:
|
||||
case MachineOperand::MO_UnextendedImmed:
|
||||
case MachineOperand::MO_PCRelativeDisp:
|
||||
break; // nothing to do for immediate fields
|
||||
|
||||
default:
|
||||
assert(0 && "Unknown machine operand type in SchedGraph builder");
|
||||
break;
|
||||
}
|
||||
default:
|
||||
assert(0 && "Unknown machine operand type in SchedGraph builder");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Add edges for values implicitly used by the machine instruction.
|
||||
// Examples include function arguments to a Call instructions or the return
|
||||
@ -655,13 +650,13 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
|
||||
MI.implicitRefIsDefinedAndUsed(i))
|
||||
if (const Instruction *srcI =
|
||||
dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
|
||||
{
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addEdgesForValue(node, I->second, srcI,
|
||||
MI.implicitRefIsDefined(i),
|
||||
MI.implicitRefIsDefinedAndUsed(i), target);
|
||||
}
|
||||
{
|
||||
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
||||
if (I != valueToDefVecMap.end())
|
||||
addEdgesForValue(node, I->second, srcI,
|
||||
MI.implicitRefIsDefined(i),
|
||||
MI.implicitRefIsDefinedAndUsed(i), target);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -683,32 +678,32 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
|
||||
//
|
||||
const MachineInstr& minstr = *node->getMachineInstr();
|
||||
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
|
||||
{
|
||||
const MachineOperand& mop = minstr.getOperand(i);
|
||||
|
||||
// if this references a register other than the hardwired
|
||||
// "zero" register, record the reference.
|
||||
if (mop.getType() == MachineOperand::MO_MachineRegister)
|
||||
{
|
||||
const MachineOperand& mop = minstr.getOperand(i);
|
||||
|
||||
// if this references a register other than the hardwired
|
||||
// "zero" register, record the reference.
|
||||
if (mop.getType() == MachineOperand::MO_MachineRegister)
|
||||
{
|
||||
int regNum = mop.getMachineRegNum();
|
||||
if (regNum != target.getRegInfo().getZeroRegNum())
|
||||
regToRefVecMap[mop.getMachineRegNum()].push_back(
|
||||
std::make_pair(node, i));
|
||||
continue; // nothing more to do
|
||||
}
|
||||
|
||||
// ignore all other non-def operands
|
||||
if (! minstr.operandIsDefined(i))
|
||||
continue;
|
||||
|
||||
// We must be defining a value.
|
||||
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
|
||||
mop.getType() == MachineOperand::MO_CCRegister)
|
||||
&& "Do not expect any other kind of operand to be defined!");
|
||||
|
||||
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
|
||||
valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
|
||||
int regNum = mop.getMachineRegNum();
|
||||
if (regNum != target.getRegInfo().getZeroRegNum())
|
||||
regToRefVecMap[mop.getMachineRegNum()]
|
||||
.push_back(std::make_pair(node, i));
|
||||
continue; // nothing more to do
|
||||
}
|
||||
|
||||
// ignore all other non-def operands
|
||||
if (! minstr.operandIsDefined(i))
|
||||
continue;
|
||||
|
||||
// We must be defining a value.
|
||||
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
|
||||
mop.getType() == MachineOperand::MO_CCRegister)
|
||||
&& "Do not expect any other kind of operand to be defined!");
|
||||
|
||||
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
|
||||
valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
|
||||
}
|
||||
|
||||
//
|
||||
// Collect value defs. for implicit operands. The interface to extract
|
||||
@ -903,18 +898,17 @@ std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
|
||||
|
||||
if (node.getMachineInstr() == NULL)
|
||||
os << "(Dummy node)\n";
|
||||
else
|
||||
{
|
||||
os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
|
||||
os << node.inEdges.size() << " Incoming Edges:\n";
|
||||
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
|
||||
os << std::string(16, ' ') << *node.inEdges[i];
|
||||
else {
|
||||
os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
|
||||
os << node.inEdges.size() << " Incoming Edges:\n";
|
||||
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
|
||||
os << std::string(16, ' ') << *node.inEdges[i];
|
||||
|
||||
os << std::string(12, ' ') << node.outEdges.size()
|
||||
<< " Outgoing Edges:\n";
|
||||
for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
|
||||
os << std::string(16, ' ') << *node.outEdges[i];
|
||||
}
|
||||
os << std::string(12, ' ') << node.outEdges.size()
|
||||
<< " Outgoing Edges:\n";
|
||||
for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
|
||||
os << std::string(16, ' ') << *node.outEdges[i];
|
||||
}
|
||||
|
||||
return os;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user