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Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC

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llvm-svn: 344774
This commit is contained in:
Fangrui Song 2018-10-19 06:12:02 +00:00
parent 57387db2a5
commit db2f6ced8d
10 changed files with 39 additions and 51 deletions
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7
lib/CodeGen/AsmPrinter/DwarfExpression.cpp
View File

@ -254,10 +254,9 @@ bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
// Don't emit locations that cannot be expressed without DW_OP_stack_value.
if (DwarfVersion < 4)
if (std::any_of(ExprCursor.begin(), ExprCursor.end(),
[](DIExpression::ExprOperand Op) -> bool {
return Op.getOp() == dwarf::DW_OP_stack_value;
})) {
if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
return Op.getOp() == dwarf::DW_OP_stack_value;
})) {
DwarfRegs.clear();
LocationKind = Unknown;
return false;

19
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -5084,12 +5084,9 @@ AArch64InstrInfo::getOutliningCandidateInfo(
unsigned FrameID = MachineOutlinerDefault;
unsigned NumBytesToCreateFrame = 4;
bool HasBTI =
std::any_of(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
[](outliner::Candidate &C) {
return C.getMF()->getFunction().hasFnAttribute(
"branch-target-enforcement");
});
bool HasBTI = any_of(RepeatedSequenceLocs, [](outliner::Candidate &C) {
return C.getMF()->getFunction().hasFnAttribute("branch-target-enforcement");
});
// If the last instruction in any candidate is a terminator, then we should
// tail call all of the candidates.
@ -5124,10 +5121,9 @@ AArch64InstrInfo::getOutliningCandidateInfo(
// LR is live, so we need to save it. Decide whether it should be saved to
// the stack, or if it can be saved to a register.
else {
if (std::all_of(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
[this](outliner::Candidate &C) {
return findRegisterToSaveLRTo(C);
})) {
if (all_of(RepeatedSequenceLocs, [this](outliner::Candidate &C) {
return findRegisterToSaveLRTo(C);
})) {
// Every candidate has an available callee-saved register for the save.
// We can save LR to a register.
FrameID = MachineOutlinerRegSave;
@ -5195,8 +5191,7 @@ AArch64InstrInfo::getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const {
unsigned Flags = 0x0;
// Check if there's a call inside this MachineBasicBlock. If there is, then
// set a flag.
if (std::any_of(MBB.begin(), MBB.end(),
[](MachineInstr &MI) { return MI.isCall(); }))
if (any_of(MBB, [](MachineInstr &MI) { return MI.isCall(); }))
Flags |= MachineOutlinerMBBFlags::HasCalls;
// Check if LR is available through all of the MBB. If it's not, then set

2
lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
View File

@ -2360,7 +2360,7 @@ bool HexagonLoopIdiomRecognize::runOnLoopBlock(Loop *CurLoop, BasicBlock *BB,
auto DominatedByBB = [this,BB] (BasicBlock *EB) -> bool {
return DT->dominates(BB, EB);
};
if (!std::all_of(ExitBlocks.begin(), ExitBlocks.end(), DominatedByBB))
if (!all_of(ExitBlocks, DominatedByBB))
return false;
bool MadeChange = false;

21
lib/Transforms/InstCombine/InstCombinePHI.cpp
View File

@ -211,23 +211,20 @@ Instruction *InstCombiner::FoldIntegerTypedPHI(PHINode &PN) {
}
// If it requires a conversion for every PHI operand, do not do it.
if (std::all_of(AvailablePtrVals.begin(), AvailablePtrVals.end(),
[&](Value *V) {
return (V->getType() != IntToPtr->getType()) ||
isa<IntToPtrInst>(V);
}))
if (all_of(AvailablePtrVals, [&](Value *V) {
return (V->getType() != IntToPtr->getType()) || isa<IntToPtrInst>(V);
}))
return nullptr;
// If any of the operand that requires casting is a terminator
// instruction, do not do it.
if (std::any_of(AvailablePtrVals.begin(), AvailablePtrVals.end(),
[&](Value *V) {
if (V->getType() == IntToPtr->getType())
return false;
if (any_of(AvailablePtrVals, [&](Value *V) {
if (V->getType() == IntToPtr->getType())
return false;
auto *Inst = dyn_cast<Instruction>(V);
return Inst && Inst->isTerminator();
}))
auto *Inst = dyn_cast<Instruction>(V);
return Inst && Inst->isTerminator();
}))
return nullptr;
PHINode *NewPtrPHI = PHINode::Create(

7
lib/Transforms/Scalar/CallSiteSplitting.cpp
View File

@ -461,10 +461,9 @@ static bool tryToSplitOnPredicatedArgument(CallSite CS, DominatorTree *DT) {
PredsCS.push_back({Pred, Conditions});
}
if (std::all_of(PredsCS.begin(), PredsCS.end(),
[](const std::pair<BasicBlock *, ConditionsTy> &P) {
return P.second.empty();
}))
if (all_of(PredsCS, [](const std::pair<BasicBlock *, ConditionsTy> &P) {
return P.second.empty();
}))
return false;
splitCallSite(CS, PredsCS, DT);

2
tools/llvm-dwarfdump/llvm-dwarfdump.cpp
View File

@ -624,7 +624,7 @@ int main(int argc, char **argv) {
if (Verify) {
// If we encountered errors during verify, exit with a non-zero exit status.
if (!std::all_of(Objects.begin(), Objects.end(), [&](std::string Object) {
if (!all_of(Objects, [&](std::string Object) {
return handleFile(Object, verifyObjectFile, OS);
}))
exit(1);

10
tools/llvm-exegesis/lib/Analysis.cpp
View File

@ -657,11 +657,11 @@ llvm::Error Analysis::run<Analysis::PrintSchedClassInconsistencies>(
// Print any scheduling class that has at least one cluster that does not
// match the checked-in data.
if (std::all_of(SchedClassClusters.begin(), SchedClassClusters.end(),
[this, &RSCAndPoints](const SchedClassCluster &C) {
return C.measurementsMatch(*SubtargetInfo_,
RSCAndPoints.RSC, Clustering_);
}))
if (llvm::all_of(SchedClassClusters,
[this, &RSCAndPoints](const SchedClassCluster &C) {
return C.measurementsMatch(
*SubtargetInfo_, RSCAndPoints.RSC, Clustering_);
}))
continue; // Nothing weird.
OS << "<div class=\"inconsistency\"><p>Sched Class <span "

2
tools/llvm-exegesis/lib/MCInstrDescView.cpp
View File

@ -174,7 +174,7 @@ const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
}
bool Instruction::hasMemoryOperands() const {
return std::any_of(Operands.begin(), Operands.end(), [](const Operand &Op) {
return any_of(Operands, [](const Operand &Op) {
return Op.isReg() && Op.isExplicit() && Op.isMemory();
});
}

13
tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp
View File

@ -218,13 +218,12 @@ void ResourceManager::releaseBuffers(ArrayRef<uint64_t> Buffers) {
}
bool ResourceManager::canBeIssued(const InstrDesc &Desc) const {
return std::all_of(Desc.Resources.begin(), Desc.Resources.end(),
[&](const std::pair<uint64_t, const ResourceUsage> &E) {
unsigned NumUnits =
E.second.isReserved() ? 0U : E.second.NumUnits;
unsigned Index = getResourceStateIndex(E.first);
return Resources[Index]->isReady(NumUnits);
});
return all_of(
Desc.Resources, [&](const std::pair<uint64_t, const ResourceUsage> &E) {
unsigned NumUnits = E.second.isReserved() ? 0U : E.second.NumUnits;
unsigned Index = getResourceStateIndex(E.first);
return Resources[Index]->isReady(NumUnits);
});
}
// Returns true if all resources are in-order, and there is at least one

7
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -2415,10 +2415,9 @@ static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info, raw_ostream &
static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {
OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "
"RegisterClass) {\n";
if (std::none_of(Info.Classes.begin(), Info.Classes.end(),
[](const ClassInfo &CI) {
return CI.isRegisterClass() && !CI.DiagnosticType.empty();
})) {
if (none_of(Info.Classes, [](const ClassInfo &CI) {
return CI.isRegisterClass() && !CI.DiagnosticType.empty();
})) {
OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
} else {
OS << " switch (RegisterClass) {\n";