diff --git a/test/CodeGen/AArch64/aarch64-load-ext.ll b/test/CodeGen/AArch64/aarch64-load-ext.ll
index 1bbab3879dc..ec585264688 100644
--- a/test/CodeGen/AArch64/aarch64-load-ext.ll
+++ b/test/CodeGen/AArch64/aarch64-load-ext.ll
@@ -102,6 +102,56 @@ define <4 x i8> @test4(<4 x i8>* %v4i8_ptr) {
   ret <4 x i8> %v4i8
 }
 
+define <2 x i32> @fsext_v2i32(<2 x i8>* %a) {
+; CHECK-LE-LABEL: fsext_v2i32:
+; CHECK-LE:       // %bb.0:
+; CHECK-LE-NEXT:    ldrsb w8, [x0]
+; CHECK-LE-NEXT:    ldrsb w9, [x0, #1]
+; CHECK-LE-NEXT:    fmov s0, w8
+; CHECK-LE-NEXT:    mov v0.s[1], w9
+; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: fsext_v2i32:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    ldrsb w8, [x0]
+; CHECK-BE-NEXT:    ldrsb w9, [x0, #1]
+; CHECK-BE-NEXT:    fmov s0, w8
+; CHECK-BE-NEXT:    mov v0.s[1], w9
+; CHECK-BE-NEXT:    rev64 v0.2s, v0.2s
+; CHECK-BE-NEXT:    ret
+  %x = load <2 x i8>, <2 x i8>* %a
+  %y = sext <2 x i8> %x to <2 x i32>
+  ret <2 x i32> %y
+}
+
+define <3 x i32> @fsext_v3i32(<3 x i8>* %a) {
+; CHECK-LE-LABEL: fsext_v3i32:
+; CHECK-LE:       // %bb.0:
+; CHECK-LE-NEXT:    ldr s0, [x0]
+; CHECK-LE-NEXT:    zip1 v0.8b, v0.8b, v0.8b
+; CHECK-LE-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-LE-NEXT:    shl v0.4s, v0.4s, #24
+; CHECK-LE-NEXT:    sshr v0.4s, v0.4s, #24
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: fsext_v3i32:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    ldr s0, [x0]
+; CHECK-BE-NEXT:    rev32 v0.8b, v0.8b
+; CHECK-BE-NEXT:    zip1 v0.8b, v0.8b, v0.8b
+; CHECK-BE-NEXT:    rev16 v0.8b, v0.8b
+; CHECK-BE-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-BE-NEXT:    shl v0.4s, v0.4s, #24
+; CHECK-BE-NEXT:    sshr v0.4s, v0.4s, #24
+; CHECK-BE-NEXT:    rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT:    ret
+  %x = load <3 x i8>, <3 x i8>* %a
+  %y = sext <3 x i8> %x to <3 x i32>
+  ret <3 x i32> %y
+}
+
 define <4 x i32> @fsext_v4i32(<4 x i8>* %a) {
 ; CHECK-LE-LABEL: fsext_v4i32:
 ; CHECK-LE:       // %bb.0:
@@ -124,6 +174,31 @@ define <4 x i32> @fsext_v4i32(<4 x i8>* %a) {
   ret <4 x i32> %y
 }
 
+define <8 x i32> @fsext_v8i32(<8 x i8>* %a) {
+; CHECK-LE-LABEL: fsext_v8i32:
+; CHECK-LE:       // %bb.0:
+; CHECK-LE-NEXT:    ldr d0, [x0]
+; CHECK-LE-NEXT:    sshll v0.8h, v0.8b, #0
+; CHECK-LE-NEXT:    sshll2 v1.4s, v0.8h, #0
+; CHECK-LE-NEXT:    sshll v0.4s, v0.4h, #0
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: fsext_v8i32:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    ld1 { v0.8b }, [x0]
+; CHECK-BE-NEXT:    sshll v0.8h, v0.8b, #0
+; CHECK-BE-NEXT:    sshll v1.4s, v0.4h, #0
+; CHECK-BE-NEXT:    sshll2 v0.4s, v0.8h, #0
+; CHECK-BE-NEXT:    rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT:    rev64 v2.4s, v1.4s
+; CHECK-BE-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT:    ext v0.16b, v2.16b, v2.16b, #8
+; CHECK-BE-NEXT:    ret
+  %x = load <8 x i8>, <8 x i8>* %a
+  %y = sext <8 x i8> %x to <8 x i32>
+  ret <8 x i32> %y
+}
+
 define <4 x i32> @fzext_v4i32(<4 x i8>* %a) {
 ; CHECK-LE-LABEL: fzext_v4i32:
 ; CHECK-LE:       // %bb.0:
@@ -172,6 +247,53 @@ define i32 @loadExti32(<4 x i8>* %ref) {
   ret i32 %conv
 }
 
+define <2 x i16> @fsext_v2i16(<2 x i8>* %a) {
+; CHECK-LE-LABEL: fsext_v2i16:
+; CHECK-LE:       // %bb.0:
+; CHECK-LE-NEXT:    ldrsb w8, [x0]
+; CHECK-LE-NEXT:    ldrsb w9, [x0, #1]
+; CHECK-LE-NEXT:    fmov s0, w8
+; CHECK-LE-NEXT:    mov v0.s[1], w9
+; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: fsext_v2i16:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    ldrsb w8, [x0]
+; CHECK-BE-NEXT:    ldrsb w9, [x0, #1]
+; CHECK-BE-NEXT:    fmov s0, w8
+; CHECK-BE-NEXT:    mov v0.s[1], w9
+; CHECK-BE-NEXT:    rev64 v0.2s, v0.2s
+; CHECK-BE-NEXT:    ret
+  %x = load <2 x i8>, <2 x i8>* %a
+  %y = sext <2 x i8> %x to <2 x i16>
+  ret <2 x i16> %y
+}
+
+define <3 x i16> @fsext_v3i16(<3 x i8>* %a) {
+; CHECK-LE-LABEL: fsext_v3i16:
+; CHECK-LE:       // %bb.0:
+; CHECK-LE-NEXT:    ldr s0, [x0]
+; CHECK-LE-NEXT:    zip1 v0.8b, v0.8b, v0.8b
+; CHECK-LE-NEXT:    shl v0.4h, v0.4h, #8
+; CHECK-LE-NEXT:    sshr v0.4h, v0.4h, #8
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: fsext_v3i16:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    ldr s0, [x0]
+; CHECK-BE-NEXT:    rev32 v0.8b, v0.8b
+; CHECK-BE-NEXT:    zip1 v0.8b, v0.8b, v0.8b
+; CHECK-BE-NEXT:    rev16 v0.8b, v0.8b
+; CHECK-BE-NEXT:    shl v0.4h, v0.4h, #8
+; CHECK-BE-NEXT:    sshr v0.4h, v0.4h, #8
+; CHECK-BE-NEXT:    rev64 v0.4h, v0.4h
+; CHECK-BE-NEXT:    ret
+  %x = load <3 x i8>, <3 x i8>* %a
+  %y = sext <3 x i8> %x to <3 x i16>
+  ret <3 x i16> %y
+}
+
 define <4 x i16> @fsext_v4i16(<4 x i8>* %a) {
 ; CHECK-LE-LABEL: fsext_v4i16:
 ; CHECK-LE:       // %bb.0:
@@ -192,6 +314,48 @@ define <4 x i16> @fsext_v4i16(<4 x i8>* %a) {
   ret <4 x i16> %y
 }
 
+define <8 x i16> @fsext_v8i16(<8 x i8>* %a) {
+; CHECK-LE-LABEL: fsext_v8i16:
+; CHECK-LE:       // %bb.0:
+; CHECK-LE-NEXT:    ldr d0, [x0]
+; CHECK-LE-NEXT:    sshll v0.8h, v0.8b, #0
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: fsext_v8i16:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    ld1 { v0.8b }, [x0]
+; CHECK-BE-NEXT:    sshll v0.8h, v0.8b, #0
+; CHECK-BE-NEXT:    rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT:    ret
+  %x = load <8 x i8>, <8 x i8>* %a
+  %y = sext <8 x i8> %x to <8 x i16>
+  ret <8 x i16> %y
+}
+
+define <16 x i16> @fsext_v16i16(<16 x i8>* %a) {
+; CHECK-LE-LABEL: fsext_v16i16:
+; CHECK-LE:       // %bb.0:
+; CHECK-LE-NEXT:    ldr q0, [x0]
+; CHECK-LE-NEXT:    sshll2 v1.8h, v0.16b, #0
+; CHECK-LE-NEXT:    sshll v0.8h, v0.8b, #0
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: fsext_v16i16:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    ld1 { v0.16b }, [x0]
+; CHECK-BE-NEXT:    sshll v1.8h, v0.8b, #0
+; CHECK-BE-NEXT:    sshll2 v0.8h, v0.16b, #0
+; CHECK-BE-NEXT:    rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT:    rev64 v2.8h, v1.8h
+; CHECK-BE-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT:    ext v0.16b, v2.16b, v2.16b, #8
+; CHECK-BE-NEXT:    ret
+  %x = load <16 x i8>, <16 x i8>* %a
+  %y = sext <16 x i8> %x to <16 x i16>
+  ret <16 x i16> %y
+}
+
 define <4 x i16> @fzext_v4i16(<4 x i8>* %a) {
 ; CHECK-LE-LABEL: fzext_v4i16:
 ; CHECK-LE:       // %bb.0: