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https://github.com/RPCS3/llvm-mirror.git
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Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
llvm-svn: 48042
This commit is contained in:
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afeac8050d
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@ -591,6 +591,11 @@ namespace ISD {
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// TRAP - Trapping instruction
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// TRAP - Trapping instruction
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TRAP,
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TRAP,
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// PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are
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// their first operand. The other operands are the address to prefetch,
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// read / write specifier, and locality specifier.
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PREFETCH,
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// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
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// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
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// store-store, device)
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// store-store, device)
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// This corresponds to the memory.barrier intrinsic.
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// This corresponds to the memory.barrier intrinsic.
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@ -1142,6 +1142,24 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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}
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break;
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break;
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case ISD::PREFETCH:
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assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
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switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
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Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
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Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
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break;
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case TargetLowering::Expand:
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// It's a noop.
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Result = LegalizeOp(Node->getOperand(0));
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break;
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}
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break;
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case ISD::MEMBARRIER: {
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case ISD::MEMBARRIER: {
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assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
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assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
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switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
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switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
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@ -3788,6 +3788,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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return "<<Unknown Target Node>>";
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return "<<Unknown Target Node>>";
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}
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}
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case ISD::PREFETCH: return "Prefetch";
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case ISD::MEMBARRIER: return "MemBarrier";
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case ISD::MEMBARRIER: return "MemBarrier";
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case ISD::ATOMIC_LCS: return "AtomicLCS";
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case ISD::ATOMIC_LCS: return "AtomicLCS";
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case ISD::ATOMIC_LAS: return "AtomicLAS";
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case ISD::ATOMIC_LAS: return "AtomicLAS";
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@ -2996,10 +2996,6 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
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DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
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return 0;
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return 0;
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}
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}
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case Intrinsic::prefetch:
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// FIXME: Currently discarding prefetches.
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return 0;
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case Intrinsic::var_annotation:
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case Intrinsic::var_annotation:
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// Discard annotate attributes
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// Discard annotate attributes
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return 0;
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return 0;
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@ -3050,6 +3046,16 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
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DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
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return 0;
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return 0;
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}
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}
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case Intrinsic::prefetch: {
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SDOperand Ops[4];
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Ops[0] = getRoot();
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Ops[1] = getValue(I.getOperand(1));
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Ops[2] = getValue(I.getOperand(2));
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Ops[3] = getValue(I.getOperand(3));
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DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
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return 0;
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}
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case Intrinsic::memory_barrier: {
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case Intrinsic::memory_barrier: {
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SDOperand Ops[6];
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SDOperand Ops[6];
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Ops[0] = getRoot();
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Ops[0] = getRoot();
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@ -211,6 +211,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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if (!Subtarget->hasV6Ops()) {
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if (!Subtarget->hasV6Ops()) {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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@ -117,6 +117,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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// We want to legalize GlobalAddress and ConstantPool and
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// We want to legalize GlobalAddress and ConstantPool and
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// ExternalSymbols nodes into the appropriate instructions to
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// ExternalSymbols nodes into the appropriate instructions to
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@ -321,6 +321,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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// Cell SPU has instructions for converting between i64 and fp.
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// Cell SPU has instructions for converting between i64 and fp.
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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@ -110,6 +110,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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// Thread Local Storage
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// Thread Local Storage
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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@ -85,6 +85,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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@ -82,6 +82,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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// PowerPC has no SREM/UREM instructions
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// PowerPC has no SREM/UREM instructions
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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@ -197,6 +197,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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@ -185,7 +185,11 @@ def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
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SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
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SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
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]>;
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]>;
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def STDMemBarrier : SDTypeProfile<0, 5, [
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def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
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SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
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]>;
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def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
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SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
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SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
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SDTCisInt<0>
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SDTCisInt<0>
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]>;
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]>;
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@ -340,15 +344,20 @@ def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
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def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
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def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
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def trap : SDNode<"ISD::TRAP" , SDTNone,
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def trap : SDNode<"ISD::TRAP" , SDTNone,
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[SDNPHasChain, SDNPSideEffect]>;
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[SDNPHasChain, SDNPSideEffect]>;
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def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
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def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
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[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
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def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
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[SDNPHasChain, SDNPSideEffect]>;
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[SDNPHasChain, SDNPSideEffect]>;
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// Do not use atomic_* directly, use atomic_*_size (see below)
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// Do not use atomic_* directly, use atomic_*_size (see below)
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def atomic_lcs : SDNode<"ISD::ATOMIC_LCS", STDAtomic3,
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def atomic_lcs : SDNode<"ISD::ATOMIC_LCS" , STDAtomic3,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def atomic_las : SDNode<"ISD::ATOMIC_LAS", STDAtomic2,
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def atomic_las : SDNode<"ISD::ATOMIC_LAS" , STDAtomic2,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
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def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
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// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
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// and truncst (see below).
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// and truncst (see below).
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@ -287,6 +287,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MEMSET , MVT::Other, Custom);
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setOperationAction(ISD::MEMSET , MVT::Other, Custom);
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setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
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setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
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if (!Subtarget->hasSSE1())
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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if (!Subtarget->hasSSE2())
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if (!Subtarget->hasSSE2())
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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@ -939,12 +939,15 @@ def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"movmskpd\t{$src, $dst|$dst, $src}",
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"movmskpd\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
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[(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
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// Prefetching loads.
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// Prefetch intrinsic.
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// TODO: no intrinsics for these?
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def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
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def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), "prefetcht0\t$src", []>;
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"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
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def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), "prefetcht1\t$src", []>;
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def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
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def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), "prefetcht2\t$src", []>;
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"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
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def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), "prefetchnta\t$src", []>;
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def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
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"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
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def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
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"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
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// Non-temporal stores
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// Non-temporal stores
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def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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15
test/CodeGen/X86/prefetch.ll
Normal file
15
test/CodeGen/X86/prefetch.ll
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@ -0,0 +1,15 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetchnta
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetcht0
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetcht1
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetcht2
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define void @t(i8* %ptr) nounwind {
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entry:
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32) nounwind
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