RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity

[X86] Disassembler support for having an ADSIZE prefix affect instructions with 0xf2 and 0xf3 prefixes.

Browse Source 
Needed to support umonitor from D45253.

llvm-svn: 329327
This commit is contained in:
Craig Topper 2018-04-05 18:20:14 +00:00
parent 44af3c40f2
commit dbad6a134b
4 changed files with 32 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/Support/X86DisassemblerDecoderCommon.h
View File

@ -93,6 +93,10 @@ enum attributeBits {
"operands change width") \
ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
"change width; overrides IC_OPSIZE") \
ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
@ -106,6 +110,8 @@ enum attributeBits {
ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \
ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \
ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \
ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \
"opcode") \
ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \

3
lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
View File

@ -964,6 +964,9 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
attrMask |= ATTR_ADSIZE;
break;
}
if (insn->hasAdSize)
attrMask |= ATTR_ADSIZE;
}
if (insn->rexPrefix & 0x08) {

21
utils/TableGen/X86DisassemblerTables.cpp
View File

@ -112,6 +112,10 @@ static inline bool inheritsFrom(InstructionContext child,
return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
case IC_XS_OPSIZE:
return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
case IC_XD_ADSIZE:
return inheritsFrom(child, IC_64BIT_XD_ADSIZE);
case IC_XS_ADSIZE:
return inheritsFrom(child, IC_64BIT_XS_ADSIZE);
case IC_64BIT_REXW:
return((noPrefix && inheritsFrom(child, IC_64BIT_REXW_XS, noPrefix)) ||
(noPrefix && inheritsFrom(child, IC_64BIT_REXW_XD, noPrefix)) ||
@ -122,12 +126,17 @@ static inline bool inheritsFrom(InstructionContext child,
(!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) ||
(!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE));
case IC_64BIT_XD:
return(inheritsFrom(child, IC_64BIT_REXW_XD));
return(inheritsFrom(child, IC_64BIT_REXW_XD) ||
(!AdSize64 && inheritsFrom(child, IC_64BIT_XD_ADSIZE)));
case IC_64BIT_XS:
return(inheritsFrom(child, IC_64BIT_REXW_XS));
return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
(!AdSize64 && inheritsFrom(child, IC_64BIT_XS_ADSIZE)));
case IC_64BIT_XD_OPSIZE:
case IC_64BIT_XS_OPSIZE:
return false;
case IC_64BIT_XD_ADSIZE:
case IC_64BIT_XS_ADSIZE:
return false;
case IC_64BIT_REXW_XD:
case IC_64BIT_REXW_XS:
case IC_64BIT_REXW_OPSIZE:
@ -953,8 +962,12 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
o << "IC_64BIT_REXW_ADSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
o << "IC_64BIT_XD_OPSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_ADSIZE))
o << "IC_64BIT_XD_ADSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
o << "IC_64BIT_XS_OPSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_ADSIZE))
o << "IC_64BIT_XS_ADSIZE";
else if ((index & ATTR_64BIT) && (index & ATTR_XS))
o << "IC_64BIT_XS";
else if ((index & ATTR_64BIT) && (index & ATTR_XD))
@ -974,6 +987,10 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
o << "IC_XS_OPSIZE";
else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
o << "IC_XD_OPSIZE";
else if ((index & ATTR_XS) && (index & ATTR_ADSIZE))
o << "IC_XS_ADSIZE";
else if ((index & ATTR_XD) && (index & ATTR_ADSIZE))
o << "IC_XD_ADSIZE";
else if (index & ATTR_XS)
o << "IC_XS";
else if (index & ATTR_XD)

4
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -324,6 +324,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_XD_OPSIZE;
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
insnContext = IC_XS_OPSIZE;
else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
insnContext = IC_XD_ADSIZE;
else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
insnContext = IC_XS_ADSIZE;
else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
insnContext = IC_OPSIZE_ADSIZE;
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)