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[mips] Fix the definition of sync, synci

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Also, fix the disassembly of synci for microMIPS.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45870

llvm-svn: 330810
This commit is contained in:
Simon Dardis 2018-04-25 10:19:22 +00:00
parent 517a29f95b
commit dbed0f6c1f
15 changed files with 78 additions and 18 deletions
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18
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -305,6 +305,11 @@ static DecodeStatus DecodeSyncI(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSynciR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@ -1649,6 +1654,19 @@ static DecodeStatus DecodeSyncI(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSynciR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,

2
lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -1127,7 +1127,7 @@ class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
bit HasSideEffects = 1;
}
class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
let DecoderMethod = "DecodeSynciR6";
}

5
lib/Target/Mips/MicroMipsInstrFormats.td
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@ -600,8 +600,9 @@ class SYNC_FM_MM : MMArch {
}
class SYNCI_FM_MM : MMArch {
bits<5> rs;
bits<16> offset;
bits<21> addr;
bits<5> rs = addr{20-16};
bits<16> offset = addr{15-0};
bits<32> Inst;
let Inst{31-26} = 0b010000;

11
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -128,6 +128,7 @@ def mem_mm_16 : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncodingMMImm16";
let DecoderMethod = "DecodeMemMMImm16";
let ParserMatchClass = MipsMemSimm16AsmOperand;
let OperandType = "OPERAND_MEMORY";
}
@ -960,11 +961,13 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
}
def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch, ISA_MICROMIPS;
let DecoderNamespace = "MicroMips" in {
let Predicates = [InMicroMips] in {
/// Control Instructions
def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
def SYNCI_MM : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM;
def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS;
let DecoderMethod = "DecodeSyncI_MM" in
def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
ISA_MICROMIPS32_NOT_MIPS32R6;
let Predicates = [InMicroMips] in {
def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
@ -1222,6 +1225,8 @@ let Predicates = [InMicroMips] in {
(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS;
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS;
defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS;

11
lib/Target/Mips/MipsInstrInfo.td
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@ -1657,8 +1657,8 @@ class SYNC_FT<string opstr> :
InstSE<(outs), (ins uimm5:$stype), "sync $stype",
[(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>;
class SYNCI_FT<string opstr> :
InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
class SYNCI_FT<string opstr, DAGOperand MO> :
InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [],
II_SYNCI, FrmOther, opstr> {
let hasSideEffects = 1;
let DecoderMethod = "DecodeSyncI";
@ -2050,7 +2050,8 @@ let DecoderNamespace = "COP3_" in {
}
def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci", mem_simm16>, SYNCI_FM,
ISA_MIPS32R2;
}
let AdditionalPredicates = [NotInMicroMips] in {
@ -2641,8 +2642,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
ISA_MIPS32R2;
}
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync",
(SYNC 0), 1>, ISA_MIPS2;
let AdditionalPredicates = [NotInMicroMips] in
def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"mulo $rs, $rt",
(MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,

2
test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
View File

@ -224,3 +224,5 @@
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x07 0x00 0x7c 0x6b # CHECK: sync 7
0x03 0x42 0x00 0x04 # CHECK: synci 1024($3)

13
test/MC/Mips/micromips/valid.s
View File

@ -282,7 +282,12 @@ bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x4
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM
bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x88,0xff,0xf6]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM
sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
sync 0 # CHECK: sync 0 # encoding: [0x00,0x00,0x6b,0x7c]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c]
synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x00,0x00,0x40]
sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC_MM
sync 0 # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC_MM
sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC_MM
synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x05,0x00,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI_MM

5
test/MC/Mips/mips32r2/valid.s
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@ -283,7 +283,9 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
@ -323,7 +325,8 @@ a:
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1:

5
test/MC/Mips/mips32r3/valid.s
View File

@ -283,7 +283,9 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
@ -323,7 +325,8 @@ a:
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1:

3
test/MC/Mips/mips32r5/valid.s
View File

@ -284,7 +284,9 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
@ -325,6 +327,7 @@ a:
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1:

4
test/MC/Mips/mips32r6/valid.s
View File

@ -220,7 +220,9 @@ a:
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
@ -248,6 +250,8 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1:

4
test/MC/Mips/mips64r2/valid.s
View File

@ -350,7 +350,9 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
@ -392,6 +394,8 @@ a:
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
1:

4
test/MC/Mips/mips64r3/valid.s
View File

@ -337,7 +337,9 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
@ -379,6 +381,8 @@ a:
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1:

4
test/MC/Mips/mips64r5/valid.s
View File

@ -345,7 +345,9 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
@ -387,6 +389,8 @@ a:
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1:

5
test/MC/Mips/mips64r6/valid.s
View File

@ -254,7 +254,9 @@ a:
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
@ -282,7 +284,8 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1:
# Check that we accept traditional %relocation(symbol) offsets for stores