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- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.

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- Teach spiller to modify DBG_VALUE instructions to reference spill slots.

llvm-svn: 102323
This commit is contained in:
Evan Cheng 2010-04-26 07:38:55 +00:00
parent d27eedab6d
commit dc0ce1eae8
10 changed files with 69 additions and 47 deletions
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14
include/llvm/Target/TargetInstrInfo.h
View File

@ -23,6 +23,7 @@ class CalleeSavedInfo;
class LiveVariables;
class MCAsmInfo;
class MachineMemOperand;
class MDNode;
class SDNode;
class SelectionDAG;
class TargetRegisterClass;
@ -361,6 +362,19 @@ public:
return false;
}
/// emitFrameIndexDebugValue - Emit a target-dependent form of
/// DBG_VALUE encoding the address of a frame index. Addresses would
/// normally be lowered the same way as other addresses on the target,
/// e.g. in load instructions. For targets that do not support this
/// the debug info is simply lost.
virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
unsigned FrameIx,
uint64_t Offset,
const MDNode *MDPtr,
DebugLoc dl) const {
return 0;
}
/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
/// slot into the specified machine instruction for the specified operand(s).
/// If this is possible, a new instruction is returned with the specified

10
include/llvm/Target/TargetLowering.h
View File

@ -1255,16 +1255,6 @@ public:
return SDValue();
}
/// EmitTargetCodeForFrameDebugValue - Emit a target-dependent form of
/// DBG_VALUE encoding the address of a frame index. Addresses would
/// normally be lowered the same way as other addresses on the target,
/// e.g. in load instructions. For targets that do not support this
/// the debug info is simply lost.
virtual void
EmitTargetCodeForFrameDebugValue(MachineBasicBlock* BB, unsigned FrameIx,
uint64_t Offset, MDNode *MDPtr,
DebugLoc dl) const {}
/// LowerOperationWrapper - This callback is invoked by the type legalizer
/// to legalize nodes with an illegal operand type but legal result types.
/// It replaces the LowerOperation callback in the type Legalizer.

18
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -1296,9 +1296,23 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
MachineOperand &O = ri.getOperand();
++ri;
if (MI->isDebugValue()) {
// Remove debug info for now.
O.setReg(0U);
// Modify DBG_VALUE now that the value is in a spill slot.
uint64_t Offset = MI->getOperand(1).getImm();
const MDNode *MDPtr = MI->getOperand(2).getMetadata();
DebugLoc DL = MI->getDebugLoc();
MachineInstr *NewDV = tii_->emitFrameIndexDebugValue(*mf_, Slot, Offset,
MDPtr, DL);
if (NewDV) {
DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
ReplaceMachineInstrInMaps(MI, NewDV);
MachineBasicBlock *MBB = MI->getParent();
MBB->insert(MBB->erase(MI), NewDV);
} else {
DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent();
}
continue;
}
assert(!O.isImplicit() && "Spilling register that's used as implicit use?");

4
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -507,7 +507,6 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
///
MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
MachineBasicBlock *InsertBB,
DenseMap<SDValue, unsigned> &VRBaseMap,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
uint64_t Offset = SD->getOffset();
@ -518,8 +517,7 @@ MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
// Stack address; this needs to be lowered in target-dependent fashion.
// EmitTargetCodeForFrameDebugValue is responsible for allocation.
unsigned FrameIx = SD->getFrameIx();
TLI->EmitTargetCodeForFrameDebugValue(InsertBB, FrameIx, Offset, MDPtr, DL);
return 0;
return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
}
// Otherwise, we're going to create an instruction here.
const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);

1
lib/CodeGen/SelectionDAG/InstrEmitter.h
View File

@ -103,7 +103,6 @@ public:
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
///
MachineInstr *EmitDbgValue(SDDbgValue *SD,
MachineBasicBlock *InsertBB,
DenseMap<SDValue, unsigned> &VRBaseMap,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);

11
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -449,9 +449,11 @@ static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
continue;
unsigned DVOrder = DVs[i]->getOrder();
if (DVOrder == ++Order) {
MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap, EM);
if (DbgMI) {
Orders.push_back(std::make_pair(DVOrder, DbgMI));
BB->insert(InsertPos, DbgMI);
}
DVs[i]->setIsInvalidated();
}
}
@ -540,7 +542,8 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
#endif
if ((*DI)->isInvalidated())
continue;
MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);
MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap, EM);
if (DbgMI) {
if (!LastOrder)
// Insert to start of the BB (after PHIs).
BB->insert(BBBegin, DbgMI);
@ -549,6 +552,7 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
MIBB->insert(llvm::next(Pos), DbgMI);
}
}
}
LastOrder = Order;
LastMI = MI;
}
@ -558,7 +562,8 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
MachineBasicBlock *InsertBB = Emitter.getBlock();
MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
if (!(*DI)->isInvalidated()) {
MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM);
MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap, EM);
if (DbgMI)
InsertBB->insert(Pos, DbgMI);
}
++DI;

13
lib/Target/X86/X86ISelLowering.cpp
View File

@ -8622,19 +8622,6 @@ X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
return BB;
}
void
X86TargetLowering::EmitTargetCodeForFrameDebugValue(MachineBasicBlock* BB,
unsigned FrameIx, uint64_t Offset,
MDNode *MDPtr, DebugLoc DL) const {
// Target dependent DBG_VALUE. Only the frame index case is done here.
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
X86AddressMode AM;
AM.BaseType = X86AddressMode::FrameIndexBase;
AM.Base.FrameIndex = FrameIx;
addFullAddress(BuildMI(BB, DL, TII->get(X86::DBG_VALUE)), AM).
addImm(Offset).addMetadata(MDPtr);
}
MachineBasicBlock *
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB,

5
lib/Target/X86/X86ISelLowering.h
View File

@ -453,11 +453,6 @@ namespace llvm {
/// and some i16 instructions are slow.
virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
virtual void
EmitTargetCodeForFrameDebugValue(MachineBasicBlock* BB,
unsigned FrameIx, uint64_t Offset,
MDNode *MDPtr, DebugLoc DL) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;

14
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2319,6 +2319,20 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
return true;
}
MachineInstr*
X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
unsigned FrameIx, uint64_t Offset,
const MDNode *MDPtr,
DebugLoc DL) const {
// Target dependent DBG_VALUE. Only the frame index case is done here.
X86AddressMode AM;
AM.BaseType = X86AddressMode::FrameIndexBase;
AM.Base.FrameIndex = FrameIx;
MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
return &*MIB;
}
static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
const SmallVectorImpl<MachineOperand> &MOs,
MachineInstr *MI,

6
lib/Target/X86/X86InstrInfo.h
View File

@ -623,6 +623,12 @@ public:
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const;
virtual
MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
unsigned FrameIx, uint64_t Offset,
const MDNode *MDPtr,
DebugLoc DL) const;
/// foldMemoryOperand - If this target supports it, fold a load or store of
/// the specified stack slot into the specified machine instruction for the
/// specified operand(s). If this is possible, the target should perform the