mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
[Hexagon] Use isMetaInstruction instead of isDebugValue
llvm-svn: 310601
This commit is contained in:
parent
cbad8b88a2
commit
dc31ae02da
@ -253,7 +253,8 @@ static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg,
|
||||
const TargetRegisterInfo *TRI) {
|
||||
return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
|
||||
MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
|
||||
MI.hasUnmodeledSideEffects() || MI.isInlineAsm() || MI.isDebugValue();
|
||||
MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||
|
||||
MI.isMetaInstruction();
|
||||
}
|
||||
|
||||
static unsigned UseReg(const MachineOperand& MO) {
|
||||
|
@ -539,7 +539,7 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const {
|
||||
return 0u;
|
||||
unsigned T = std::count_if(B->begin(), B->getFirstTerminator(),
|
||||
[](const MachineInstr &MI) {
|
||||
return !MI.isDebugValue();
|
||||
return !MI.isMetaInstruction();
|
||||
});
|
||||
if (T < HEXAGON_PACKET_SIZE)
|
||||
Spare += HEXAGON_PACKET_SIZE-T;
|
||||
|
@ -138,7 +138,7 @@ bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
|
||||
MachineBasicBlock::iterator MIE = MBB.end();
|
||||
while (MII != MIE) {
|
||||
InstOffset += HII->getSize(*MII);
|
||||
if (MII->isDebugValue()) {
|
||||
if (MII->isMetaInstruction()) {
|
||||
++MII;
|
||||
continue;
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user