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MachineInst support mapping SDNode fast math flags for support in Back End code generation
Summary: Machine Instruction flags for fast math support and MIR print support Reviewers: spatel, arsenm Reviewed By: arsenm Subscribers: wdng Differential Revision: https://reviews.llvm.org/D45781 llvm-svn: 331417
This commit is contained in:
Michael Berg
parent
3c3f64c605
commit
dc3d19e5de
@ -80,7 +80,21 @@ public:
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FrameDestroy = 1 << 1, // Instruction is used as a part of
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// function frame destruction code.
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BundledPred = 1 << 2, // Instruction has bundled predecessors.
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BundledSucc = 1 << 3 // Instruction has bundled successors.
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BundledSucc = 1 << 3, // Instruction has bundled successors.
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FmNoNans = 1 << 4, // Instruction does not support Fast
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// math nan values.
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FmNoInfs = 1 << 5, // Instruction does not support Fast
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// math infinity values.
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FmNsz = 1 << 6, // Instruction is not required to retain
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// signed zero values.
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FmArcp = 1 << 7, // Instruction supports Fast math
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// reciprocal approximations.
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FmContract = 1 << 8, // Instruction supports Fast math
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// contraction operations like fma.
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FmAfn = 1 << 9, // Instruction may map to Fast math
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// instrinsic approximation.
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FmReassoc = 1 << 10 // Instruction supports Fast math
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// reassociation of operand order.
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};
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private:
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@ -93,7 +107,7 @@ private:
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using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
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OperandCapacity CapOperands; // Capacity of the Operands array.
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uint8_t Flags = 0; // Various bits of additional
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uint16_t Flags = 0; // Various bits of additional
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// information about machine
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// instruction.
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@ -186,7 +200,7 @@ public:
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/// Set a MI flag.
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void setFlag(MIFlag Flag) {
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Flags |= (uint8_t)Flag;
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Flags |= (uint16_t)Flag;
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}
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void setFlags(unsigned flags) {
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@ -197,7 +211,7 @@ public:
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/// clearFlag - Clear a MI flag.
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void clearFlag(MIFlag Flag) {
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Flags &= ~((uint8_t)Flag);
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Flags &= ~((uint16_t)Flag);
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}
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/// Return true if MI is in a bundle (but not the first MI in a bundle).
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@ -212,6 +212,13 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
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.Case("tied-def", MIToken::kw_tied_def)
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.Case("frame-setup", MIToken::kw_frame_setup)
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.Case("frame-destroy", MIToken::kw_frame_destroy)
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.Case("nnan", MIToken::kw_nnan)
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.Case("ninf", MIToken::kw_ninf)
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.Case("nsz", MIToken::kw_nsz)
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.Case("arcp", MIToken::kw_arcp)
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.Case("contract", MIToken::kw_contract)
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.Case("afn", MIToken::kw_afn)
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.Case("reassoc", MIToken::kw_reassoc)
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.Case("debug-location", MIToken::kw_debug_location)
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.Case("same_value", MIToken::kw_cfi_same_value)
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.Case("offset", MIToken::kw_cfi_offset)
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@ -64,6 +64,13 @@ struct MIToken {
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kw_tied_def,
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kw_frame_setup,
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kw_frame_destroy,
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kw_nnan,
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kw_ninf,
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kw_nsz,
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kw_arcp,
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kw_contract,
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kw_afn,
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kw_reassoc,
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kw_debug_location,
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kw_cfi_same_value,
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kw_cfi_offset,
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@ -936,13 +936,36 @@ bool MIParser::verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
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}
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bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
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// Allow both:
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// * frame-setup frame-destroy OPCODE
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// * frame-destroy frame-setup OPCODE
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// Allow frame and fast math flags for OPCODE
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while (Token.is(MIToken::kw_frame_setup) ||
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Token.is(MIToken::kw_frame_destroy)) {
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Flags |= Token.is(MIToken::kw_frame_setup) ? MachineInstr::FrameSetup
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: MachineInstr::FrameDestroy;
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Token.is(MIToken::kw_frame_destroy) ||
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Token.is(MIToken::kw_nnan) ||
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Token.is(MIToken::kw_ninf) ||
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Token.is(MIToken::kw_nsz) ||
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Token.is(MIToken::kw_arcp) ||
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Token.is(MIToken::kw_contract) ||
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Token.is(MIToken::kw_afn) ||
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Token.is(MIToken::kw_reassoc)) {
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// Mine frame and fast math flags
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if (Token.is(MIToken::kw_frame_setup))
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Flags |= MachineInstr::FrameSetup;
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if (Token.is(MIToken::kw_frame_destroy))
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Flags |= MachineInstr::FrameDestroy;
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if (Token.is(MIToken::kw_nnan))
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Flags |= MachineInstr::FmNoNans;
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if (Token.is(MIToken::kw_ninf))
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Flags |= MachineInstr::FmNoInfs;
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if (Token.is(MIToken::kw_nsz))
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Flags |= MachineInstr::FmNsz;
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if (Token.is(MIToken::kw_arcp))
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Flags |= MachineInstr::FmArcp;
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if (Token.is(MIToken::kw_contract))
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Flags |= MachineInstr::FmContract;
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if (Token.is(MIToken::kw_afn))
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Flags |= MachineInstr::FmAfn;
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if (Token.is(MIToken::kw_reassoc))
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Flags |= MachineInstr::FmReassoc;
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lex();
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}
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if (Token.isNot(MIToken::Identifier))
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@ -680,6 +680,20 @@ void MIPrinter::print(const MachineInstr &MI) {
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OS << "frame-setup ";
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if (MI.getFlag(MachineInstr::FrameDestroy))
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OS << "frame-destroy ";
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if (MI.getFlag(MachineInstr::FmNoNans))
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OS << "nnan ";
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if (MI.getFlag(MachineInstr::FmNoInfs))
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OS << "ninf ";
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if (MI.getFlag(MachineInstr::FmNsz))
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OS << "nsz ";
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if (MI.getFlag(MachineInstr::FmArcp))
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OS << "arcp ";
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if (MI.getFlag(MachineInstr::FmContract))
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OS << "contract ";
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if (MI.getFlag(MachineInstr::FmAfn))
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OS << "afn ";
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if (MI.getFlag(MachineInstr::FmReassoc))
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OS << "reassoc ";
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OS << TII->getName(MI.getOpcode());
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if (I < E)
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@ -1302,6 +1302,20 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
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OS << "frame-setup ";
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if (getFlag(MachineInstr::FrameDestroy))
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OS << "frame-destroy ";
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if (getFlag(MachineInstr::FmNoNans))
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OS << "nnan ";
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if (getFlag(MachineInstr::FmNoInfs))
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OS << "ninf ";
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if (getFlag(MachineInstr::FmNsz))
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OS << "nsz ";
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if (getFlag(MachineInstr::FmArcp))
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OS << "arcp ";
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if (getFlag(MachineInstr::FmContract))
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OS << "contract ";
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if (getFlag(MachineInstr::FmAfn))
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OS << "afn ";
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if (getFlag(MachineInstr::FmReassoc))
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OS << "reassoc ";
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// Print the opcode name.
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if (TII)
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36
test/CodeGen/MIR/X86/fastmath.mir
Normal file
36
test/CodeGen/MIR/X86/fastmath.mir
Normal file
@ -0,0 +1,36 @@
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# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses the fast math instruction flags.
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...
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---
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name: baz
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body: |
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bb.0.entry:
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liveins: $xmm0
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; CHECK: %0:fr32 = COPY $xmm0
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%0:fr32 = COPY $xmm0
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; CHECK: %1:fr32 = nnan VMULSSrr %0, %0
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%1:fr32 = nnan VMULSSrr %0, %0
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; CHECK: %2:fr32 = ninf VMULSSrr %1, %1
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%2:fr32 = ninf VMULSSrr %1, %1
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; CHECK: %3:fr32 = nsz VMULSSrr %2, %2
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%3:fr32 = nsz VMULSSrr %2, %2
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; CHECK: %4:fr32 = arcp VMULSSrr %3, %3
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%4:fr32 = arcp VMULSSrr %3, %3
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; CHECK: %5:fr32 = contract VMULSSrr %4, %4
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%5:fr32 = contract VMULSSrr %4, %4
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; CHECK: %6:fr32 = afn VMULSSrr %5, %5
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%6:fr32 = afn VMULSSrr %5, %5
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; CHECK: %7:fr32 = reassoc VMULSSrr %6, %6
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%7:fr32 = reassoc VMULSSrr %6, %6
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; CHECK: %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7
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%8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7
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; CHECK: %9:fr32 = contract afn reassoc VMULSSrr %8, %8
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%9:fr32 = contract afn reassoc VMULSSrr %8, %8
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; CHECK: $xmm0 = COPY %9
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$xmm0 = COPY %9
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; CHECK: RET 0, $xmm0
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RET 0, $xmm0
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...
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