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ExecutionDepsFix refactoring:
- Changing DenseMap<MBB*, LiveReg*> to SmallVector<LiveReg*> - Now the MBB number will be the index of LiveReg in the vector. - Adding asserts This patch is NFC. This is the one of multiple patches that fix bugzilla https://bugs.llvm.org/show_bug.cgi?id=33869 Most of the patches are intended at refactoring the existent code. Additional relevant reviews: https://reviews.llvm.org/D40330 https://reviews.llvm.org/D40332 https://reviews.llvm.org/D40333 https://reviews.llvm.org/D40334 Differential Revision: https://reviews.llvm.org/D40331 Change-Id: If4a3f141693d0361ddb292432337dbb63a1e69ee llvm-svn: 323089
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@ -144,7 +144,7 @@ private:
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MBBInfo() = default;
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};
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using MBBInfoMap = DenseMap<MachineBasicBlock *, MBBInfo>;
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using MBBInfoMap = SmallVector<MBBInfo, 4>;
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MBBInfoMap MBBInfos;
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public:
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@ -179,7 +179,7 @@ private:
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// Keeps clearance information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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using OutRegsInfoMap = DenseMap<MachineBasicBlock *, LiveReg *>;
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using OutRegsInfoMap = SmallVector<LiveReg *, 4>;
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OutRegsInfoMap MBBOutRegsInfos;
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/// Current instruction number.
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@ -249,7 +249,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
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// Keeps domain information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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using OutRegsInfoMap = DenseMap<MachineBasicBlock *, LiveReg *>;
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using OutRegsInfoMap = SmallVector<LiveReg *, 4>;
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OutRegsInfoMap MBBOutRegsInfos;
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ReachingDefAnalysis *RDA;
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@ -179,6 +179,7 @@ void ReachingDefAnalysis::enterBasicBlock(
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MachineBasicBlock *MBB = TraversedMBB.MBB;
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int MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number.");
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MBBReachingDefs[MBBNumber].resize(NumRegUnits);
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// Reset instruction counter in each basic block.
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@ -209,10 +210,9 @@ void ReachingDefAnalysis::enterBasicBlock(
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock* pred : MBB->predecessors()) {
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auto fi = MBBOutRegsInfos.find(pred);
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assert(fi != MBBOutRegsInfos.end() &&
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assert(pred->getNumber() < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveReg *Incoming = fi->second;
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LiveReg *Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming == nullptr)
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@ -253,10 +253,9 @@ void ExecutionDomainFix::enterBasicBlock(
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock* pred : MBB->predecessors()) {
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auto fi = MBBOutRegsInfos.find(pred);
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assert(fi != MBBOutRegsInfos.end() &&
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assert(pred->getNumber() < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveReg *Incoming = fi->second;
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LiveReg *Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming == nullptr)
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@ -295,8 +294,10 @@ void ExecutionDomainFix::enterBasicBlock(
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void ReachingDefAnalysis::leaveBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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assert(LiveRegs && "Must enter basic block first.");
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int MBBNumber = TraversedMBB.MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number.");
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// Save register clearances at end of MBB - used by enterBasicBlock().
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MBBOutRegsInfos[TraversedMBB.MBB] = LiveRegs;
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MBBOutRegsInfos[MBBNumber] = LiveRegs;
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// While processing the basic block, we kept `Def` relative to the start
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// of the basic block for convenience. However, future use of this information
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@ -310,9 +311,11 @@ void ReachingDefAnalysis::leaveBasicBlock(
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void ExecutionDomainFix::leaveBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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assert(LiveRegs && "Must enter basic block first.");
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LiveReg *OldOutRegs = MBBOutRegsInfos[TraversedMBB.MBB];
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int MBBNumber = TraversedMBB.MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number.");
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LiveReg *OldOutRegs = MBBOutRegsInfos[MBBNumber];
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// Save register clearances at end of MBB - used by enterBasicBlock().
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MBBOutRegsInfos[TraversedMBB.MBB] = LiveRegs;
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MBBOutRegsInfos[MBBNumber] = LiveRegs;
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if (OldOutRegs) {
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// This must be the second pass.
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// Release all the DomainValues instead of keeping them.
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@ -445,6 +448,7 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
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assert(!MI->isDebugValue() && "Won't process debug values");
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int MBBNumber = MI->getParent()->getNumber();
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assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number.");
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const MCInstrDesc &MCID = MI->getDesc();
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for (unsigned i = 0,
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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@ -714,18 +718,17 @@ void BreakFalseDeps::processBasicBlock(MachineBasicBlock* MBB) {
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}
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bool LoopTraversal::isBlockDone(MachineBasicBlock *MBB) {
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return MBBInfos[MBB].PrimaryCompleted &&
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MBBInfos[MBB].IncomingCompleted == MBBInfos[MBB].PrimaryIncoming &&
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MBBInfos[MBB].IncomingProcessed == MBB->pred_size();
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int MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBInfos.size() && "Unexpected basic block number.");
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return MBBInfos[MBBNumber].PrimaryCompleted &&
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MBBInfos[MBBNumber].IncomingCompleted == MBBInfos[MBBNumber].PrimaryIncoming &&
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MBBInfos[MBBNumber].IncomingProcessed == MBB->pred_size();
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}
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LoopTraversal::TraversalOrder
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LoopTraversal::traverse(MachineFunction &MF) {
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// Initialize the MMBInfos
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for (MachineBasicBlock &MBB : MF) {
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MBBInfo InitialInfo;
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MBBInfos.insert(std::make_pair(&MBB, InitialInfo));
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}
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MBBInfos.assign(MF.getNumBlockIDs(), MBBInfo());
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/*
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* We want to visit every instruction in every basic block in order to update
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@ -762,8 +765,10 @@ LoopTraversal::traverse(MachineFunction &MF) {
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for (MachineBasicBlock *MBB : RPOT) {
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// N.B: IncomingProcessed and IncomingCompleted were already updated while
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// processing this block's predecessors.
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MBBInfos[MBB].PrimaryCompleted = true;
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MBBInfos[MBB].PrimaryIncoming = MBBInfos[MBB].IncomingProcessed;
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int MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBInfos.size() && "Unexpected basic block number.");
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MBBInfos[MBBNumber].PrimaryCompleted = true;
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MBBInfos[MBBNumber].PrimaryIncoming = MBBInfos[MBBNumber].IncomingProcessed;
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bool Primary = true;
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Workqueue.push_back(MBB);
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while (!Workqueue.empty()) {
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@ -772,11 +777,13 @@ LoopTraversal::traverse(MachineFunction &MF) {
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bool Done = isBlockDone(ActiveMBB);
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MBBTraversalOrder.push_back(TraversedMBBInfo(ActiveMBB, Primary, Done));
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for (MachineBasicBlock *Succ : ActiveMBB->successors()) {
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int SuccNumber = Succ->getNumber();
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assert(SuccNumber < MBBInfos.size() && "Unexpected basic block number.");
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if (!isBlockDone(Succ)) {
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if (Primary)
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MBBInfos[Succ].IncomingProcessed++;
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MBBInfos[SuccNumber].IncomingProcessed++;
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if (Done)
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MBBInfos[Succ].IncomingCompleted++;
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MBBInfos[SuccNumber].IncomingCompleted++;
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if (isBlockDone(Succ))
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Workqueue.push_back(Succ);
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}
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@ -838,9 +845,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
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}
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// Initialize the MBBOutRegsInfos
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for (MachineBasicBlock &MBB : mf) {
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MBBOutRegsInfos.insert(std::make_pair(&MBB, nullptr));
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}
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MBBOutRegsInfos.assign(mf.getNumBlockIDs(), nullptr);
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// Traverse the basic blocks.
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LoopTraversal Traversal;
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@ -850,12 +855,12 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
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}
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for (auto MBBOutRegs : MBBOutRegsInfos) {
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if (!MBBOutRegs.second)
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if (!MBBOutRegs)
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continue;
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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if (MBBOutRegs.second[i].Value)
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release(MBBOutRegs.second[i].Value);
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delete[] MBBOutRegs.second;
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if (MBBOutRegs[i].Value)
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release(MBBOutRegs[i].Value);
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delete[] MBBOutRegs;
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}
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MBBOutRegsInfos.clear();
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Avail.clear();
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@ -879,9 +884,7 @@ bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");
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// Initialize the MBBOutRegsInfos
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for (MachineBasicBlock &MBB : mf) {
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MBBOutRegsInfos.insert(std::make_pair(&MBB, nullptr));
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}
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MBBOutRegsInfos.assign(mf.getNumBlockIDs(), nullptr);
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// Traverse the basic blocks.
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LoopTraversal Traversal;
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@ -902,9 +905,9 @@ bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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void ReachingDefAnalysis::releaseMemory() {
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// Clear the LiveOuts vectors and collapse any remaining DomainValues.
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for (auto MBBOutRegs : MBBOutRegsInfos) {
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if (!MBBOutRegs.second)
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if (!MBBOutRegs)
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continue;
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delete[] MBBOutRegs.second;
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delete[] MBBOutRegs;
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}
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MBBOutRegsInfos.clear();
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MBBReachingDefs.clear();
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@ -932,9 +935,11 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
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}
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int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
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assert(InstIds.count(MI) && "Unexpected machine instuction.");
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int InstId = InstIds[MI];
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int DefRes = ReachingDedDefaultVal;
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int MBBNumber = MI->getParent()->getNumber();
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assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number.");
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int LatestDef = ReachingDedDefaultVal;
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for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
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for (int Def : MBBReachingDefs[MBBNumber][*Unit]) {
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@ -948,5 +953,6 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
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}
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int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) {
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assert(InstIds.count(MI) && "Unexpected machine instuction.");
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return InstIds[MI] - getReachingDef(MI, PhysReg);
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}
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