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AMDGPU/GlobalISel: Cleanup legality for extensions

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llvm-svn: 351691
This commit is contained in:
Matt Arsenault 2019-01-20 18:34:24 +00:00
parent ee885e4c8d
commit dc75546ec1
5 changed files with 236 additions and 12 deletions
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16
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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@ -140,6 +140,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor({{S32, S64}});
getActionDefinitionsBuilder(G_FPEXT)
.legalFor({{S64, S32}, {S32, S16}})
.lowerFor({{S64, S16}}); // FIXME: Implement
// Use actual fsub instruction
setAction({G_FSUB, S32}, Legal);
@ -150,16 +154,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
setAction({G_FCMP, 1, S32}, Legal);
setAction({G_FCMP, 1, S64}, Legal);
setAction({G_ZEXT, S64}, Legal);
setAction({G_ZEXT, 1, S32}, Legal);
setAction({G_SEXT, S64}, Legal);
setAction({G_SEXT, 1, S32}, Legal);
setAction({G_ANYEXT, S64}, Legal);
setAction({G_ANYEXT, S32}, Legal);
setAction({G_ANYEXT, 1, S32}, Legal);
setAction({G_ANYEXT, 1, S16}, Legal);
getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalFor({{S64, S32}, {S32, S16}, {S64, S16}});
setAction({G_FPTOSI, S32}, Legal);
setAction({G_FPTOSI, 1, S32}, Legal);

65
test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir Normal file
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@ -0,0 +1,65 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_anyext_s32_to_s64
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_s32_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_anyext_s16_to_s64
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s64) = G_ANYEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: test_anyext_s16_to_s32
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_anyext_i1_to_s32
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...

34
test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir Normal file
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@ -0,0 +1,34 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_fpext_f16_to_f32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fpext_f16_to_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK: $vgpr0 = COPY [[FPEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_FPEXT %1
$vgpr0 = COPY %2
...
---
name: test_fpext_f32_to_f64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fpext_f32_to_f64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[FPEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_FPEXT %0
$vgpr0_vgpr1 = COPY %1
...

72
test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir Normal file
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@ -0,0 +1,72 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_sext_s32_to_s64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s32_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_SEXT %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_sext_s16_to_s64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s16)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s64) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: test_sext_s16_to_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2
...
---
name: test_sext_i1_to_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_sext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2
...

61
test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
View File

@ -2,13 +2,70 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_zext_i32_to_i64
name: test_zext_s32_to_s64
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_i32_to_i64
; CHECK-LABEL: name: test_zext_s32_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_ZEXT %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_zext_s16_to_s64
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s64) = G_ZEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: test_zext_s16_to_s32
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...
---
name: test_zext_i1_to_s32
body: |
bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...