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[FPEnv][ARM] Don't call mutateStrictFPToFP when lowering

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mutateStrictFPToFP can delete the node and replace it with another with the same
value which can later cause problems, and returning the result of
mutateStrictFPToFP doesn't work because SelectionDAGLegalize expects that the
returned value has the same number of results as the original. Instead handle
things by doing the mutation manually.

Differential Revision: https://reviews.llvm.org/D74726
This commit is contained in:
John Brawn 2020-02-17 16:55:32 +00:00
parent 2271f86e27
commit dc7cf72780
2 changed files with 55 additions and 2 deletions
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12
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -5425,7 +5425,12 @@ SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
// FIXME: Remove this when we have strict fp instruction selection patterns
if (IsStrict) {
DAG.mutateStrictFPToFP(Op.getNode());
SDLoc Loc(Op);
SDValue Result =
DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
: ISD::FP_TO_UINT,
Loc, Op.getValueType(), SrcVal);
return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
}
return Op;
@ -16532,7 +16537,10 @@ SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
if (SrcSz == 32 && DstSz == 64 && Subtarget->hasFP64()) {
// FIXME: Remove this when we have strict fp instruction selection patterns
if (IsStrict) {
DAG.mutateStrictFPToFP(Op.getNode());
SDLoc Loc(Op);
SDValue Result = DAG.getNode(ISD::FP_EXTEND,
Loc, Op.getValueType(), SrcVal);
return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
}
return Op;
}

45
test/CodeGen/ARM/fp-intrinsics.ll
View File

@ -72,6 +72,21 @@ define i32 @fptosi_f32(float %x) #0 {
ret i32 %val
}
; CHECK-LABEL: fptosi_f32_twice:
; CHECK-NOSP: bl __aeabi_f2iz
; CHECK-NOSP: bl __aeabi_f2iz
; CHECK-SP: vcvt.s32.f32
; FIXME-CHECK-SP: vcvt.s32.f32
define void @fptosi_f32_twice(float %arg, i32* %ptr) #0 {
entry:
%conv = call i32 @llvm.experimental.constrained.fptosi.f32(float %arg, metadata !"fpexcept.strict") #0
store i32 %conv, i32* %ptr, align 4
%conv1 = call i32 @llvm.experimental.constrained.fptosi.f32(float %arg, metadata !"fpexcept.strict") #0
%idx = getelementptr inbounds i32, i32* %ptr, i32 1
store i32 %conv1, i32* %idx, align 4
ret void
}
; CHECK-LABEL: fptoui_f32:
; CHECK-NOSP: bl __aeabi_f2uiz
; FIXME-CHECK-SP: vcvt.u32.f32
@ -80,6 +95,21 @@ define i32 @fptoui_f32(float %x) #0 {
ret i32 %val
}
; CHECK-LABEL: fptoui_f32_twice:
; CHECK-NOSP: bl __aeabi_f2uiz
; CHECK-NOSP: bl __aeabi_f2uiz
; FIXME-CHECK-SP: vcvt.u32.f32
; FIXME-CHECK-SP: vcvt.u32.f32
define void @fptoui_f32_twice(float %arg, i32* %ptr) #0 {
entry:
%conv = call i32 @llvm.experimental.constrained.fptoui.f32(float %arg, metadata !"fpexcept.strict") #0
store i32 %conv, i32* %ptr, align 4
%conv1 = call i32 @llvm.experimental.constrained.fptoui.f32(float %arg, metadata !"fpexcept.strict") #0
%idx = getelementptr inbounds i32, i32* %ptr, i32 1
store i32 %conv1, i32* %idx, align 4
ret void
}
; CHECK-LABEL: sqrt_f32:
; CHECK-NOSP: bl sqrtf
; CHECK-SP: vsqrt.f32
@ -947,6 +977,21 @@ define double @fpext_f32(float %x) #0 {
ret double %val
}
; CHECK-LABEL: fpext_f32_twice:
; CHECK-NODP: bl __aeabi_f2d
; CHECK-NODP: bl __aeabi_f2d
; CHECK-DP: vcvt.f64.f32
; FIXME-CHECK-DP: vcvt.f64.f32
define void @fpext_f32_twice(float %arg, double* %ptr) #0 {
entry:
%conv1 = call double @llvm.experimental.constrained.fpext.f64.f32(float %arg, metadata !"fpexcept.strict") #0
store double %conv1, double* %ptr, align 8
%conv2 = call double @llvm.experimental.constrained.fpext.f64.f32(float %arg, metadata !"fpexcept.strict") #0
%idx = getelementptr inbounds double, double* %ptr, i32 1
store double %conv2, double* %idx, align 8
ret void
}
; CHECK-LABEL: sitofp_f32_i32:
; CHECK-NOSP: bl __aeabi_i2f
; FIXME-CHECK-SP: vcvt.f32.s32