mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
Move physreg dependency generation into aptly named addPhysRegDeps.
llvm-svn: 148173
This commit is contained in:
Andrew Trick
parent
1fd0adb573
commit
dcb9435036
@ -37,7 +37,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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bool IsPostRAFlag)
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: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
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InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
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Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
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UnitLatencies(false), Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
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LoopRegs(MLI, MDT), FirstDbgValue(0) {
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DbgValues.clear();
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}
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@ -52,6 +52,9 @@ void ScheduleDAGInstrs::Run(MachineBasicBlock *bb,
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Begin = begin;
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InsertPosIndex = endcount;
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// Check to see if the scheduler cares about latencies.
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UnitLatencies = ForceUnitLatencies();
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ScheduleDAG::Run(bb, end);
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}
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@ -181,6 +184,172 @@ void ScheduleDAGInstrs::AddSchedBarrierDeps() {
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}
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}
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/// addPhysRegDeps - Add register dependencies (data, anti, and output) from
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/// this SUnit to following instructions in the same scheduling region that
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/// depend the physical register referenced at OperIdx.
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void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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const MachineOperand &MO = MI->getOperand(OperIdx);
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unsigned Reg = MO.getReg();
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// Ask the target if address-backscheduling is desirable, and if so how much.
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
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// Optionally add output and anti dependencies. For anti
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// dependencies we use a latency of 0 because for a multi-issue
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// target we want to allow the defining instruction to issue
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// in the same cycle as the using instruction.
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// TODO: Using a latency of 1 here for output dependencies assumes
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// there's no cost for reusing registers.
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SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
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for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &DefList = Defs[*Alias];
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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if (DefSU == &ExitSU)
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continue;
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if (DefSU != SU &&
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(*Alias))) {
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if (Kind == SDep::Anti)
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DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
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else {
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unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
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DefSU->getInstr());
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DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
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}
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}
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}
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}
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// Retrieve the UseList to add data dependencies and update uses.
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std::vector<SUnit *> &UseList = Uses[Reg];
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if (MO.isDef()) {
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// Update DefList. Defs are pushed in the order they are visited and
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// never reordered.
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std::vector<SUnit *> &DefList = Defs[Reg];
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// Add any data dependencies.
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unsigned DataLatency = SU->Latency;
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU == SU)
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continue;
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unsigned LDataLatency = DataLatency;
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// Optionally add in a special extra latency for nodes that
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// feed addresses.
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// TODO: Do this for register aliases too.
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// TODO: Perhaps we should get rid of
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// SpecialAddressLatency and just move this into
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// adjustSchedDependency for the targets that care about it.
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if (SpecialAddressLatency != 0 && !UnitLatencies &&
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UseSU != &ExitSU) {
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MachineInstr *UseMI = UseSU->getInstr();
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
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assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
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if (RegUseIndex >= 0 &&
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(UseMI->mayLoad() || UseMI->mayStore()) &&
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(unsigned)RegUseIndex < UseMCID.getNumOperands() &&
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UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
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LDataLatency += SpecialAddressLatency;
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}
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// Adjust the dependence latency using operand def/use
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// information (if any), and then allow the target to
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// perform its own adjustments.
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const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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}
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UseSU->addPred(dep);
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU == SU)
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continue;
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const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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}
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UseSU->addPred(dep);
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}
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}
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// If a def is going to wrap back around to the top of the loop,
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// backschedule it.
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if (!UnitLatencies && DefList.empty()) {
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LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
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if (I != LoopRegs.Deps.end()) {
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const MachineOperand *UseMO = I->second.first;
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unsigned Count = I->second.second;
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const MachineInstr *UseMI = UseMO->getParent();
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unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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// TODO: If we knew the total depth of the region here, we could
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// handle the case where the whole loop is inside the region but
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// is large enough that the isScheduleHigh trick isn't needed.
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if (UseMOIdx < UseMCID.getNumOperands()) {
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// Currently, we only support scheduling regions consisting of
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// single basic blocks. Check to see if the instruction is in
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// the same region by checking to see if it has the same parent.
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if (UseMI->getParent() != MI->getParent()) {
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unsigned Latency = SU->Latency;
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if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
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Latency += SpecialAddressLatency;
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// This is a wild guess as to the portion of the latency which
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// will be overlapped by work done outside the current
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// scheduling region.
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Latency -= std::min(Latency, Count);
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// Add the artificial edge.
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ExitSU.addPred(SDep(SU, SDep::Order, Latency,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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} else if (SpecialAddressLatency > 0 &&
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UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
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// The entire loop body is within the current scheduling region
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// and the latency of this operation is assumed to be greater
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// than the latency of the loop.
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// TODO: Recursively mark data-edge predecessors as
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// isScheduleHigh too.
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SU->isScheduleHigh = true;
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}
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}
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LoopRegs.Deps.erase(I);
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}
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}
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UseList.clear();
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if (!MO.isDead())
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DefList.clear();
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// Calls will not be reordered because of chain dependencies (see
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// below). Since call operands are dead, calls may continue to be added
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// to the DefList making dependence checking quadratic in the size of
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// the block. Instead, we leave only one call at the back of the
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// DefList.
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if (SU->isCall) {
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while (!DefList.empty() && DefList.back()->isCall)
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DefList.pop_back();
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}
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DefList.push_back(SU);
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} else {
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UseList.push_back(SU);
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}
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}
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/// addVirtRegDeps - Add register dependencies (data, anti, and output) from
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/// this SUnit to following instructions in the same scheduling region that
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/// depend the virtual register referenced at OperIdx.
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void ScheduleDAGInstrs::addVirtRegDeps(SUnit *SU, unsigned OperIdx) {
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assert(false && "unimplemented");
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}
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void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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// We'll be allocating one SUnit for each instruction, plus one for
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// the region exit node.
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@ -199,13 +368,6 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
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std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
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// Check to see if the scheduler cares about latencies.
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bool UnitLatencies = ForceUnitLatencies();
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// Ask the target if address-backscheduling is desirable, and if so how much.
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
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// Remove any stale debug info; sometimes BuildSchedGraph is called again
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// without emitting the info from the previous call.
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DbgValues.clear();
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@ -254,153 +416,11 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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assert(!IsPostRA || TRI->isPhysicalRegister(Reg) &&
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"Virtual register encountered!");
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// Optionally add output and anti dependencies. For anti
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// dependencies we use a latency of 0 because for a multi-issue
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// target we want to allow the defining instruction to issue
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// in the same cycle as the using instruction.
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// TODO: Using a latency of 1 here for output dependencies assumes
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// there's no cost for reusing registers.
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SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
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for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &DefList = Defs[*Alias];
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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if (DefSU == &ExitSU)
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continue;
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if (DefSU != SU &&
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(*Alias))) {
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if (Kind == SDep::Anti)
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DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
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else {
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unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j,
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DefSU->getInstr());
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DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
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}
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}
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}
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}
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// Retrieve the UseList to add data dependencies and update uses.
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std::vector<SUnit *> &UseList = Uses[Reg];
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if (MO.isDef()) {
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// Update DefList. Defs are pushed in the order they are visited and
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// never reordered.
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std::vector<SUnit *> &DefList = Defs[Reg];
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// Add any data dependencies.
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unsigned DataLatency = SU->Latency;
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU == SU)
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continue;
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unsigned LDataLatency = DataLatency;
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// Optionally add in a special extra latency for nodes that
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// feed addresses.
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// TODO: Do this for register aliases too.
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// TODO: Perhaps we should get rid of
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// SpecialAddressLatency and just move this into
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// adjustSchedDependency for the targets that care about it.
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if (SpecialAddressLatency != 0 && !UnitLatencies &&
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UseSU != &ExitSU) {
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MachineInstr *UseMI = UseSU->getInstr();
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
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assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
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if (RegUseIndex >= 0 &&
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(UseMI->mayLoad() || UseMI->mayStore()) &&
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(unsigned)RegUseIndex < UseMCID.getNumOperands() &&
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UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
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LDataLatency += SpecialAddressLatency;
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}
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// Adjust the dependence latency using operand def/use
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// information (if any), and then allow the target to
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// perform its own adjustments.
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const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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}
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UseSU->addPred(dep);
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU == SU)
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continue;
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const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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}
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UseSU->addPred(dep);
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}
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}
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// If a def is going to wrap back around to the top of the loop,
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// backschedule it.
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if (!UnitLatencies && DefList.empty()) {
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LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
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if (I != LoopRegs.Deps.end()) {
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const MachineOperand *UseMO = I->second.first;
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unsigned Count = I->second.second;
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const MachineInstr *UseMI = UseMO->getParent();
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unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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// TODO: If we knew the total depth of the region here, we could
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// handle the case where the whole loop is inside the region but
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// is large enough that the isScheduleHigh trick isn't needed.
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if (UseMOIdx < UseMCID.getNumOperands()) {
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// Currently, we only support scheduling regions consisting of
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// single basic blocks. Check to see if the instruction is in
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// the same region by checking to see if it has the same parent.
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if (UseMI->getParent() != MI->getParent()) {
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unsigned Latency = SU->Latency;
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if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
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Latency += SpecialAddressLatency;
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// This is a wild guess as to the portion of the latency which
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// will be overlapped by work done outside the current
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// scheduling region.
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Latency -= std::min(Latency, Count);
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// Add the artificial edge.
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ExitSU.addPred(SDep(SU, SDep::Order, Latency,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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} else if (SpecialAddressLatency > 0 &&
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UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
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// The entire loop body is within the current scheduling region
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// and the latency of this operation is assumed to be greater
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// than the latency of the loop.
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// TODO: Recursively mark data-edge predecessors as
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// isScheduleHigh too.
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SU->isScheduleHigh = true;
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}
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}
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LoopRegs.Deps.erase(I);
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}
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}
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UseList.clear();
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if (!MO.isDead())
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DefList.clear();
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// Calls will not be reordered because of chain dependencies (see
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// below). Since call operands are dead, calls may continue to be added
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// to the DefList making dependence checking quadratic in the size of
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// the block. Instead, we leave only one call at the back of the
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// DefList.
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if (SU->isCall) {
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while (!DefList.empty() && DefList.back()->isCall)
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DefList.pop_back();
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}
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DefList.push_back(SU);
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} else {
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UseList.push_back(SU);
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if (TRI->isPhysicalRegister(Reg))
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addPhysRegDeps(SU, j);
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else {
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assert(!IsPostRA && "Virtual register encountered!");
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addVirtRegDeps(SU, j);
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}
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}
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@ -107,6 +107,9 @@ namespace llvm {
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/// isPostRA flag indicates vregs cannot be present.
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bool IsPostRA;
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/// UnitLatencies flag forces single-cycle data dependencies.
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bool UnitLatencies;
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/// Defs, Uses - Remember where defs and uses of each register are as we
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/// iterate upward through the instructions. This is allocated here instead
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/// of inside BuildSchedGraph to avoid the need for it to be initialized and
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@ -205,6 +208,10 @@ namespace llvm {
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virtual void dumpNode(const SUnit *SU) const;
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virtual std::string getGraphNodeLabel(const SUnit *SU) const;
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protected:
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void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
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void addVirtRegDeps(SUnit *SU, unsigned OperIdx);
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};
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}
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