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[Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignment

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Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jyknight, sdardis, nemanjai, javed.absar, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67229

llvm-svn: 371200
This commit is contained in:
Guillaume Chatelet 2019-09-06 12:48:34 +00:00
parent 4cee06d392
commit dcfd456e85
13 changed files with 19 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/CodeGen/TargetLowering.h
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@ -2104,9 +2104,9 @@ protected:
TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
}
/// Set the target's minimum function alignment (in log2(bytes))
void setMinFunctionLogAlignment(unsigned LogAlign) {
MinFunctionAlignment = llvm::Align(1ULL << LogAlign);
/// Set the target's minimum function alignment.
void setMinFunctionAlignment(llvm::Align Align) {
MinFunctionAlignment = Align;
}
/// Set the target's preferred function alignment. This should be set if

2
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -640,7 +640,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
EnableExtLdPromotion = true;
// Set required alignment.
setMinFunctionLogAlignment(2);
setMinFunctionAlignment(llvm::Align(4));
// Set preferred alignments.
setPrefFunctionLogAlignment(STI.getPrefFunctionLogAlignment());
setPrefLoopLogAlignment(STI.getPrefLoopLogAlignment());

3
lib/Target/ARM/ARMISelLowering.cpp
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@ -1421,7 +1421,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setPrefLoopLogAlignment(Subtarget->getPrefLoopLogAlignment());
setMinFunctionLogAlignment(Subtarget->isThumb() ? 1 : 2);
setMinFunctionAlignment(Subtarget->isThumb() ? llvm::Align(2)
: llvm::Align(4));
if (Subtarget->isThumb() || Subtarget->isThumb2())
setTargetDAGCombine(ISD::ABS);

2
lib/Target/BPF/BPFISelLowering.cpp
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@ -133,7 +133,7 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
setBooleanContents(ZeroOrOneBooleanContent);
// Function alignments (log2)
setMinFunctionLogAlignment(3);
setMinFunctionAlignment(llvm::Align(8));
setPrefFunctionLogAlignment(3);
if (BPFExpandMemcpyInOrder) {

2
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -1237,7 +1237,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setPrefLoopLogAlignment(4);
setPrefFunctionLogAlignment(4);
setMinFunctionLogAlignment(2);
setMinFunctionAlignment(llvm::Align(4));
setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
setBooleanContents(TargetLoweringBase::UndefinedBooleanContent);
setBooleanVectorContents(TargetLoweringBase::UndefinedBooleanContent);

2
lib/Target/Lanai/LanaiISelLowering.cpp
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@ -145,7 +145,7 @@ LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::XOR);
// Function alignments (log2)
setMinFunctionLogAlignment(2);
setMinFunctionAlignment(llvm::Align(4));
setPrefFunctionLogAlignment(2);
setJumpIsExpensive(true);

2
lib/Target/MSP430/MSP430ISelLowering.cpp
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@ -327,7 +327,7 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN);
// TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
setMinFunctionLogAlignment(1);
setMinFunctionAlignment(llvm::Align(2));
setPrefFunctionLogAlignment(1);
}

3
lib/Target/Mips/MipsISelLowering.cpp
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@ -518,7 +518,8 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setLibcallName(RTLIB::SRA_I128, nullptr);
}
setMinFunctionLogAlignment(Subtarget.isGP64bit() ? 3 : 2);
setMinFunctionAlignment(Subtarget.isGP64bit() ? llvm::Align(8)
: llvm::Align(4));
// The arguments on the stack are defined in terms of 4-byte slots on O32
// and 8-byte slots on N32/N64.

2
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -1180,7 +1180,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setJumpIsExpensive();
}
setMinFunctionLogAlignment(2);
setMinFunctionAlignment(llvm::Align(4));
if (Subtarget.isDarwin())
setPrefFunctionLogAlignment(4);

6
lib/Target/RISCV/RISCVISelLowering.cpp
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@ -198,9 +198,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setBooleanContents(ZeroOrOneBooleanContent);
// Function alignments (log2).
unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2;
setMinFunctionLogAlignment(FunctionAlignment);
setPrefFunctionLogAlignment(FunctionAlignment);
const llvm::Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
setMinFunctionAlignment(FunctionAlignment);
setPrefFunctionLogAlignment(Log2(FunctionAlignment));
// Effectively disable jump table generation.
setMinimumJumpTableEntries(INT_MAX);

2
lib/Target/Sparc/SparcISelLowering.cpp
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@ -1805,7 +1805,7 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
setMinFunctionLogAlignment(2);
setMinFunctionAlignment(llvm::Align(4));
computeRegisterProperties(Subtarget->getRegisterInfo());
}

2
lib/Target/SystemZ/SystemZISelLowering.cpp
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@ -120,7 +120,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
// Instructions are strings of 2-byte aligned 2-byte values.
setMinFunctionLogAlignment(2);
setMinFunctionAlignment(llvm::Align(4));
// For performance reasons we prefer 16-byte alignment.
setPrefFunctionLogAlignment(4);

2
lib/Target/XCore/XCoreISelLowering.cpp
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@ -171,7 +171,7 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::INTRINSIC_VOID);
setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
setMinFunctionLogAlignment(1);
setMinFunctionAlignment(llvm::Align(2));
setPrefFunctionLogAlignment(2);
}