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https://github.com/RPCS3/llvm-mirror.git
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ARM/ISel: Factor out isScaledConstantInRange() helper.
llvm-svn: 123823
This commit is contained in:
Daniel Dunbar
parent
305613b87a
commit
dd1dd698f0
@ -287,6 +287,28 @@ static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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isInt32Immediate(N->getOperand(1).getNode(), Imm);
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}
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/// \brief Check whether a particular node is a constant value representable as
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/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
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///
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/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
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static bool isScaledConstantInRange(SDValue Node, unsigned Scale,
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int RangeMin, int RangeMax,
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int &ScaledConstant) {
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assert(Scale && "Invalid scale!");
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// Check that this is a constant.
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const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
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if (!C)
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return false;
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ScaledConstant = (int) C->getZExtValue();
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if ((ScaledConstant % Scale) != 0)
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return false;
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ScaledConstant /= Scale;
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return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
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}
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/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
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/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
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/// least on current ARM implementations) which should be avoidded.
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@ -473,12 +495,10 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
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// Leave simple R +/- imm12 operands for LDRi12
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if (N.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC >= 0 && RHSC < 0x1000) ||
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(RHSC < 0 && RHSC > -0x1000)) // 12 bits.
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return false;
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}
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
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-0x1000+1, 0x1000, RHSC)) // 12 bits.
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return false;
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}
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if (Subtarget->isCortexA9() && !N.hasOneUse())
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@ -592,27 +612,25 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
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// Match simple R +/- imm12 operands.
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if (N.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC >= 0 && RHSC < 0x1000) ||
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(RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
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ARM_AM::no_shift),
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MVT::i32);
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return AM2_BASE;
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
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-0x1000+1, 0x1000, RHSC)) { // 12 bits.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
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ARM_AM::no_shift),
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MVT::i32);
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return AM2_BASE;
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}
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}
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@ -689,15 +707,13 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
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: cast<StoreSDNode>(Op)->getAddressingMode();
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ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
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? ARM_AM::add : ARM_AM::sub;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
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int Val = (int)C->getZExtValue();
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if (Val >= 0 && Val < 0x1000) { // 12 bits.
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
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ARM_AM::no_shift),
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MVT::i32);
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return true;
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}
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int Val;
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if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
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ARM_AM::no_shift),
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MVT::i32);
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return true;
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}
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Offset = N;
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@ -748,25 +764,23 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
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}
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// If the RHS is +/- imm8, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC >= 0 && RHSC < 256) ||
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(RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
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return true;
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
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-256 + 1, 256, RHSC)) { // 8 bits.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
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return true;
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}
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Base = N.getOperand(0);
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@ -783,13 +797,11 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
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: cast<StoreSDNode>(Op)->getAddressingMode();
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ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
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? ARM_AM::add : ARM_AM::sub;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
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int Val = (int)C->getZExtValue();
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if (Val >= 0 && Val < 256) {
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
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return true;
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}
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int Val;
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if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
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return true;
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}
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Offset = N;
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@ -815,28 +827,23 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
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}
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// If the RHS is +/- imm8, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
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RHSC >>= 2;
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if ((RHSC >= 0 && RHSC < 256) ||
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(RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
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MVT::i32);
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return true;
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}
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
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-256 + 1, 256, RHSC)) {
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
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MVT::i32);
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return true;
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}
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Base = N;
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@ -886,7 +893,6 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
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// Thumb Addressing Modes
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//===----------------------------------------------------------------------===//
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bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
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SDValue &Base, SDValue &Offset){
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// FIXME dl should come from the parent load or store, not the address
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@ -927,16 +933,12 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
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(RHSR && RHSR->getReg() == ARM::SP))
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return false;
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
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RHSC /= Scale;
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if (RHSC >= 0 && RHSC < 32)
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return false;
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}
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}
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// FIXME: Why do we explicitly check for a match here and then return false?
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// Presumably to allow something else to match, but shouldn't this be
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// documented?
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
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return false;
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Base = N.getOperand(0);
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Offset = N.getOperand(1);
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@ -1008,18 +1010,11 @@ ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
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}
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// If the RHS is + imm5 * scale, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
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RHSC /= Scale;
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if (RHSC >= 0 && RHSC < 32) {
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Base = N.getOperand(0);
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OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
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return true;
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}
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}
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
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Base = N.getOperand(0);
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OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
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return true;
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}
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Base = N.getOperand(0);
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@ -1061,20 +1056,15 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
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if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
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(LHSR && LHSR->getReg() == ARM::SP)) {
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// If the RHS is + imm8 * scale, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
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RHSC >>= 2;
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if (RHSC >= 0 && RHSC < 256) {
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
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return true;
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}
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
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return true;
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}
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}
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@ -1189,14 +1179,12 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
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ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
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? cast<LoadSDNode>(Op)->getAddressingMode()
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: cast<StoreSDNode>(Op)->getAddressingMode();
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
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int RHSC = (int)RHS->getZExtValue();
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if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
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OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
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? CurDAG->getTargetConstant(RHSC, MVT::i32)
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: CurDAG->getTargetConstant(-RHSC, MVT::i32);
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return true;
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}
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int RHSC;
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if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
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OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
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? CurDAG->getTargetConstant(RHSC, MVT::i32)
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: CurDAG->getTargetConstant(-RHSC, MVT::i32);
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return true;
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}
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return false;
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