From dd3332e2e51813be36bde1960b6e3f7c9ba420d5 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Fri, 22 Jan 2021 15:02:36 -0800 Subject: [PATCH] Change materializeFrameBaseRegister() to return register The only caller of this function is in the LocalStackSlotAllocation and it creates base register of class returned by the target's getPointerRegClass(). AMDGPU wants to use a different reg class here so let materializeFrameBaseRegister to just create and return whatever it wants. Differential Revision: https://reviews.llvm.org/D95268 --- include/llvm/CodeGen/TargetRegisterInfo.h | 10 +++++----- lib/CodeGen/LocalStackSlotAllocation.cpp | 9 +++++---- lib/Target/AArch64/AArch64RegisterInfo.cpp | 11 +++++++---- lib/Target/AArch64/AArch64RegisterInfo.h | 5 ++--- lib/Target/AMDGPU/SIRegisterInfo.cpp | 19 ++++++++++++------- lib/Target/AMDGPU/SIRegisterInfo.h | 5 ++--- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 11 +++++++---- lib/Target/ARM/ARMBaseRegisterInfo.h | 5 ++--- lib/Target/PowerPC/PPCRegisterInfo.cpp | 11 +++++++---- lib/Target/PowerPC/PPCRegisterInfo.h | 5 ++--- 10 files changed, 51 insertions(+), 40 deletions(-) diff --git a/include/llvm/CodeGen/TargetRegisterInfo.h b/include/llvm/CodeGen/TargetRegisterInfo.h index 253f71cb5f1..8790e2f09eb 100644 --- a/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/include/llvm/CodeGen/TargetRegisterInfo.h @@ -911,11 +911,11 @@ public: return false; } - /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx - /// before insertion point I. - virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, - Register BaseReg, int FrameIdx, - int64_t Offset) const { + /// Insert defining instruction(s) for a pointer to FrameIdx before + /// insertion point I. Return materialized frame pointer. + virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, + int FrameIdx, + int64_t Offset) const { llvm_unreachable("materializeFrameBaseRegister does not exist on this " "target"); } diff --git a/lib/CodeGen/LocalStackSlotAllocation.cpp b/lib/CodeGen/LocalStackSlotAllocation.cpp index ec3cce3fa1f..ec6e693e8a4 100644 --- a/lib/CodeGen/LocalStackSlotAllocation.cpp +++ b/lib/CodeGen/LocalStackSlotAllocation.cpp @@ -416,15 +416,16 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); BaseReg = Fn.getRegInfo().createVirtualRegister(RC); - LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg + LLVM_DEBUG(dbgs() << " Materializing base register" << " at frame local offset " - << LocalOffset + InstrOffset << "\n"); + << LocalOffset + InstrOffset); // Tell the target to insert the instruction to initialize // the base register. // MachineBasicBlock::iterator InsertionPt = Entry->begin(); - TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, - InstrOffset); + BaseReg = TRI->materializeFrameBaseRegister(Entry, FrameIdx, InstrOffset); + + LLVM_DEBUG(dbgs() << " into " << printReg(BaseReg, TRI) << '\n'); // The base register already includes any offset specified // by the instruction, so account for that so it doesn't get diff --git a/lib/Target/AArch64/AArch64RegisterInfo.cpp b/lib/Target/AArch64/AArch64RegisterInfo.cpp index 231e8b3089f..f90856d14b2 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -531,10 +531,10 @@ bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx /// at the beginning of the basic block. -void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, - Register BaseReg, - int FrameIdx, - int64_t Offset) const { +Register +AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, + int FrameIdx, + int64_t Offset) const { MachineBasicBlock::iterator Ins = MBB->begin(); DebugLoc DL; // Defaults to "unknown" if (Ins != MBB->end()) @@ -544,6 +544,7 @@ void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, MF.getSubtarget().getInstrInfo(); const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); + Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); @@ -551,6 +552,8 @@ void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, .addFrameIndex(FrameIdx) .addImm(Offset) .addImm(Shifter); + + return BaseReg; } void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, diff --git a/lib/Target/AArch64/AArch64RegisterInfo.h b/lib/Target/AArch64/AArch64RegisterInfo.h index 1c74d39d404..0c871ac089a 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.h +++ b/lib/Target/AArch64/AArch64RegisterInfo.h @@ -107,9 +107,8 @@ public: bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, - int FrameIdx, - int64_t Offset) const override; + Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, + int64_t Offset) const override; void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp index ecf2159c4fa..8911917cffb 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -420,10 +420,9 @@ bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { return TII->isLegalFLATOffset(FullOffset, AMDGPUAS::PRIVATE_ADDRESS, true); } -void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, - Register BaseReg, - int FrameIdx, - int64_t Offset) const { +Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, + int FrameIdx, + int64_t Offset) const { MachineBasicBlock::iterator Ins = MBB->begin(); DebugLoc DL; // Defaults to "unknown" @@ -432,16 +431,20 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, MachineFunction *MF = MBB->getParent(); const SIInstrInfo *TII = ST.getInstrInfo(); + MachineRegisterInfo &MRI = MF->getRegInfo(); unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; + Register BaseReg = MRI.createVirtualRegister( + ST.enableFlatScratch() ? &AMDGPU::SReg_32_XEXEC_HIRegClass + : &AMDGPU::VGPR_32RegClass); + if (Offset == 0) { BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg) .addFrameIndex(FrameIdx); - return; + return BaseReg; } - MachineRegisterInfo &MRI = MF->getRegInfo(); Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); Register FIReg = MRI.createVirtualRegister( @@ -457,13 +460,15 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_U32), BaseReg) .addReg(OffsetReg, RegState::Kill) .addReg(FIReg); - return; + return BaseReg; } TII->getAddNoCarry(*MBB, Ins, DL, BaseReg) .addReg(OffsetReg, RegState::Kill) .addReg(FIReg) .addImm(0); // clamp bit + + return BaseReg; } void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, diff --git a/lib/Target/AMDGPU/SIRegisterInfo.h b/lib/Target/AMDGPU/SIRegisterInfo.h index 6f0307f87bc..963da9b3536 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/lib/Target/AMDGPU/SIRegisterInfo.h @@ -94,9 +94,8 @@ public: bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, - int FrameIdx, - int64_t Offset) const override; + Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, + int64_t Offset) const override; void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 17dfe55c649..1a264dabeeb 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -640,10 +640,10 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to /// be a pointer to FrameIdx at the beginning of the basic block. -void ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, - Register BaseReg, - int FrameIdx, - int64_t Offset) const { +Register +ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, + int FrameIdx, + int64_t Offset) const { ARMFunctionInfo *AFI = MBB->getParent()->getInfo(); unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); @@ -657,6 +657,7 @@ void ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); const MCInstrDesc &MCID = TII.get(ADDriOpc); + Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) @@ -664,6 +665,8 @@ void ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, if (!AFI->isThumb1OnlyFunction()) MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); + + return BaseReg; } void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index e1fe4fa8898..5afb6c6aa01 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -168,9 +168,8 @@ public: int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override; bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, - int FrameIdx, - int64_t Offset) const override; + Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, + int64_t Offset) const override; void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 03672f40b2a..178a13443e2 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1375,10 +1375,9 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { /// Insert defining instruction(s) for BaseReg to /// be a pointer to FrameIdx at the beginning of the basic block. -void PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, - Register BaseReg, - int FrameIdx, - int64_t Offset) const { +Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, + int FrameIdx, + int64_t Offset) const { unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; MachineBasicBlock::iterator Ins = MBB->begin(); @@ -1391,10 +1390,14 @@ void PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); const MCInstrDesc &MCID = TII.get(ADDriOpc); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); + const TargetRegisterClass *RC = getPointerRegClass(MF); + Register BaseReg = MRI.createVirtualRegister(RC); MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); BuildMI(*MBB, Ins, DL, MCID, BaseReg) .addFrameIndex(FrameIdx).addImm(Offset); + + return BaseReg; } void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 8ff4c5dc58a..93f330ab56b 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -136,9 +136,8 @@ public: // Support for virtual base registers. bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; - void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, - int FrameIdx, - int64_t Offset) const override; + Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, + int64_t Offset) const override; void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override; bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,