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GlobalISel: relax type constraints on G_ICMP to allow pointers.

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llvm-svn: 281600
This commit is contained in:
Tim Northover 2016-09-15 10:40:38 +00:00
parent 337f4de87e
commit dd47cd5b6e
5 changed files with 21 additions and 5 deletions
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4
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
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@ -437,8 +437,8 @@ public:
/// \pre \p Res must be a generic virtual register with scalar or
/// vector type. Typically this starts as s1 or <N x s1>.
/// \pre \p Op0 and Op1 must be generic virtual registers with the
/// same number of elements as \p Res (or scalar, if \p Res is
/// scalar).
/// same number of elements as \p Res. If \p Res is a scalar,
/// \p Op0 must be either a scalar or pointer.
/// \pre \p Pred must be an integer predicate.
///
/// \return a MachineInstrBuilder for the newly created instruction.

4
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
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@ -321,11 +321,9 @@ MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
unsigned Res, unsigned Op0,
unsigned Op1) {
#ifndef NDEBUG
assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
"invalid operand type");
assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
if (MRI->getType(Op0).isScalar())
if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer())
assert(MRI->getType(Res).isScalar() && "type mismatch");
else
assert(MRI->getType(Res).isVector() &&

1
lib/Target/AArch64/AArch64MachineLegalizer.cpp
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@ -95,6 +95,7 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
setAction({G_ICMP, s1}, Legal);
setAction({G_ICMP, 1, s32}, Legal);
setAction({G_ICMP, 1, s64}, Legal);
setAction({G_ICMP, 1, p0}, Legal);
for (auto Ty : {s1, s8, s16}) {
setAction({G_ICMP, 1, Ty}, WidenScalar);

12
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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@ -542,6 +542,18 @@ define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
ret void
}
; CHECK-LABEL: name: ptr_comparison
; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0
; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1
; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
%res = icmp eq i8* %a, %b
store i1 %res, i1* %addr
ret void
}
; CHECK-LABEL: name: test_fadd
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1

5
test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
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@ -21,6 +21,8 @@ registers:
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
- { id: 9, class: _ }
- { id: 10, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
@ -37,4 +39,7 @@ body: |
; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3
; CHECK: %8(s1) = G_ICMP intpred(ult), [[LHS32]](s32), [[RHS32]]
%8(s1) = G_ICMP intpred(ult), %2, %3
%9(p0) = G_INTTOPTR %0(s64)
%10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0)
...