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[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions
The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
This commit is contained in:
Simon Atanasyan
parent
a01979c6b4
commit
dd563e1f3f
@ -245,12 +245,6 @@ class MipsAsmParser : public MCTargetAsmParser {
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void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI, bool IsLoad);
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void expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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void expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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@ -1326,7 +1320,7 @@ public:
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return false;
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if (!getMemBase()->isGPRAsmReg())
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return false;
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const unsigned PtrBits = 32;
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const unsigned PtrBits = AsmParser.getABI().ArePtrs64bit() ? 64 : 32;
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if (isa<MCTargetExpr>(getMemOff()) ||
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(isConstantMemOff() && isIntN(PtrBits, getConstantMemOff())))
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return true;
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@ -2143,7 +2137,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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(OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
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MCOperand &Op = Inst.getOperand(i);
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if (Op.isImm()) {
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int MemOffset = Op.getImm();
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int64_t MemOffset = Op.getImm();
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if (MemOffset < -32768 || MemOffset > 32767) {
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// Offset can't exceed 16bit value.
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expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
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@ -3569,14 +3563,6 @@ bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI, bool IsLoad) {
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if (IsLoad)
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expandLoadInst(Inst, IDLoc, Out, STI);
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else
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expandStoreInst(Inst, IDLoc, Out, STI);
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}
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void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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const MCOperand &BaseRegOp = Inst.getOperand(1);
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@ -3595,7 +3581,7 @@ void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
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(DstRegClassID == Mips::GPR64RegClassID);
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if (!IsGPR || (BaseReg == DstReg)) {
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if (!IsLoad || !IsGPR || (BaseReg == DstReg)) {
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// At this point we need AT to perform the expansions
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// and we exit if it is not available.
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TmpReg = getATReg(IDLoc);
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@ -3604,8 +3590,27 @@ void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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}
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if (OffsetOp.isImm()) {
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TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
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OffsetOp.getImm(), TmpReg, IDLoc, STI);
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int64_t LoOffset = OffsetOp.getImm() & 0xffff;
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int64_t HiOffset = OffsetOp.getImm() & ~0xffff;
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// If msb of LoOffset is 1(negative number) we must increment
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// HiOffset to account for the sign-extension of the low part.
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if (LoOffset & 0x8000)
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HiOffset += 0x10000;
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bool IsLargeOffset = HiOffset != 0;
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if (IsLargeOffset) {
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bool Is32BitImm = (HiOffset >> 32) == 0;
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if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
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IDLoc, Out, STI))
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return;
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}
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if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
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TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg,
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BaseReg, IDLoc, STI);
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TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, LoOffset, IDLoc, STI);
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} else {
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assert(OffsetOp.isExpr() && "expected expression operand kind");
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const MCExpr *ExprOffset = OffsetOp.getExpr();
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@ -3613,44 +3618,16 @@ void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
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MCOperand HiOperand = MCOperand::createExpr(
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MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext()));
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TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
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LoOperand, TmpReg, IDLoc, STI);
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if (IsLoad)
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TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
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LoOperand, TmpReg, IDLoc, STI);
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else
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TOut.emitStoreWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
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LoOperand, TmpReg, IDLoc, STI);
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}
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}
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void MipsAsmParser::expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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const MCOperand &SrcRegOp = Inst.getOperand(0);
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assert(SrcRegOp.isReg() && "expected register operand kind");
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const MCOperand &BaseRegOp = Inst.getOperand(1);
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assert(BaseRegOp.isReg() && "expected register operand kind");
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const MCOperand &OffsetOp = Inst.getOperand(2);
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned SrcReg = SrcRegOp.getReg();
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unsigned BaseReg = BaseRegOp.getReg();
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if (OffsetOp.isImm()) {
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TOut.emitStoreWithImmOffset(Inst.getOpcode(), SrcReg, BaseReg,
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OffsetOp.getImm(),
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[&]() { return getATReg(IDLoc); }, IDLoc, STI);
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return;
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}
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unsigned ATReg = getATReg(IDLoc);
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if (!ATReg)
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return;
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assert(OffsetOp.isExpr() && "expected expression operand kind");
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const MCExpr *ExprOffset = OffsetOp.getExpr();
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MCOperand LoOperand = MCOperand::createExpr(
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MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
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MCOperand HiOperand = MCOperand::createExpr(
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MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext()));
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TOut.emitStoreWithSymOffset(Inst.getOpcode(), SrcReg, BaseReg, HiOperand,
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LoOperand, ATReg, IDLoc, STI);
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}
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bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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@ -270,11 +270,10 @@ sym:
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# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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# Test ld/sd/lld with offsets exceed 16-bit size.
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# Test lb/sb/ld/sd/lld with offsets exceeding 16-bits in size.
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ld $4, 0x8000
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# CHECK: lui $4, 1
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# CHECK-NEXT: addu $4, $4, $zero
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# CHECK-NEXT: ld $4, -32768($4)
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ld $4, 0x20008($3)
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@ -282,9 +281,32 @@ sym:
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# CHECK-NEXT: addu $4, $4, $3
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# CHECK-NEXT: ld $4, 8($4)
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ld $4,0x100010004
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# CHECK: addiu $4, $zero, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ld $4, 4($4)
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ld $4,0x1800180018004
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ld $4, -32764($4)
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ld $4,0x1800180018004($3)
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: daddu $4, $4, $3
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# CHECK-NEXT: ld $4, -32764($4)
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sd $4, 0x8000
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# CHECK: lui $1, 1
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# CHECK-NEXT: addu $1, $1, $zero
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# CHECK-NEXT: sd $4, -32768($1)
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sd $4, 0x20008($3)
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@ -292,12 +314,155 @@ sym:
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# CHECK-NEXT: addu $1, $1, $3
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# CHECK-NEXT: sd $4, 8($1)
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sd $4,0x100010004
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# CHECK: addiu $1, $zero, 1
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: ori $1, $1, 1
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: sd $4, 4($1)
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sd $4,0x1800180018004
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# CHECK: lui $1, 1
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# CHECK-NEXT: ori $1, $1, 32769
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: ori $1, $1, 32770
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: sd $4, -32764($1)
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sd $4,0x1800180018004($3)
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# CHECK: lui $1, 1
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# CHECK-NEXT: ori $1, $1, 32769
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: ori $1, $1, 32770
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: daddu $1, $1, $3
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# CHECK-NEXT: sd $4, -32764($1)
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lld $4, 0x8000
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# CHECK: lui $4, 1
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# CHECK-NEXT: addu $4, $4, $zero
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# CHECK-NEXT: lld $4, -32768($4)
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lld $4, 0x20008($3)
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# CHECK: lui $4, 2
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# CHECK-NEXT: addu $4, $4, $3
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# CHECK-NEXT: lld $4, 8($4)
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lld $4,0x100010004
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# CHECK: addiu $4, $zero, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lld $4, 4($4)
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lld $4,0x1800180018004
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lld $4, -32764($4)
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lld $4,0x1800180018004($3)
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: daddu $4, $4, $3
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# CHECK-NEXT: lld $4, -32764($4)
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lb $4,0x100010004
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# CHECK: addiu $4, $zero, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lb $4, 4($4)
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lb $4,0x1800180018004
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lb $4, -32764($4)
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lb $4,0x1800180018004($3)
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: daddu $4, $4, $3
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# CHECK-NEXT: lb $4, -32764($4)
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sb $4,0x100010004
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# CHECK: addiu $1, $zero, 1
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: ori $1, $1, 1
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: sb $4, 4($1)
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sb $4,0x1800180018004
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# CHECK: lui $1, 1
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# CHECK-NEXT: ori $1, $1, 32769
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: ori $1, $1, 32770
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: sb $4, -32764($1)
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sb $4,0x1800180018004($3)
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# CHECK: lui $1, 1
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# CHECK-NEXT: ori $1, $1, 32769
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: ori $1, $1, 32770
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# CHECK-NEXT: dsll $1, $1, 16
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# CHECK-NEXT: daddu $1, $1, $3
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# CHECK-NEXT: sb $4, -32764($1)
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lh $4,0x100010004
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# CHECK: addiu $4, $zero, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lh $4, 4($4)
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lh $4,0x1800180018004
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lh $4, -32764($4)
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lh $4,0x1800180018004($3)
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: daddu $4, $4, $3
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# CHECK-NEXT: lh $4, -32764($4)
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lhu $4,0x100010004
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# CHECK: addiu $4, $zero, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 1
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lhu $4, 4($4)
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lhu $4,0x1800180018004
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: lhu $4, -32764($4)
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lhu $4,0x1800180018004($3)
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# CHECK: lui $4, 1
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# CHECK-NEXT: ori $4, $4, 32769
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: ori $4, $4, 32770
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# CHECK-NEXT: dsll $4, $4, 16
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# CHECK-NEXT: daddu $4, $4, $3
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# CHECK-NEXT: lhu $4, -32764($4)
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@ -20,12 +20,8 @@
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dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
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sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
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lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid register number
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lb $4, -2147483649($5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
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lb $4, 2147483648($5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
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lb $4, 8($32) # CHECK: :[[@LINE]]:18: error: invalid register number
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lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid register number
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lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
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lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
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lbu $4, 8($32) # CHECK: :[[@LINE]]:19: error: invalid register number
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ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
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@ -194,20 +194,21 @@ a:
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jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
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l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
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l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
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lb $24,-14515($10)
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lbu $8,30195($v1)
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ld $sp,-28645($s1)
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lb $24,-2147483649($10)
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lbu $24,-2147483649($10)
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ld $sp,-2147483649($s1)
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ldc1 $f11,16391($s0)
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ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
||||
ldl $24,-4167($24)
|
||||
ldr $14,-30358($s4)
|
||||
ldxc1 $f8,$s7($15)
|
||||
lh $11,-8556($s5)
|
||||
lhu $s3,-22851($v0)
|
||||
lh $11,-2147483649($s5)
|
||||
lhu $s3,-2147483649($v0)
|
||||
li $at,-29773
|
||||
li $zero,-29889
|
||||
ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67]
|
||||
lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70]
|
||||
lld $24,-2147483649($10)
|
||||
luxc1 $f19,$s6($s5)
|
||||
lw $8,5674($a1)
|
||||
lwc1 $f16,10225($k0)
|
||||
|
||||
@ -60,12 +60,8 @@ local_label:
|
||||
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
|
||||
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
|
||||
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
|
||||
lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
|
||||
@ -178,14 +174,8 @@ local_label:
|
||||
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
|
||||
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
|
||||
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
|
||||
ld $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
ld $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
ld $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
|
||||
lld $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
lld $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
sd $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
lld $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
|
||||
sd $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
|
||||
sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
|
||||
dsrl $2, $4, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
|
||||
dsrl $2, $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
|
||||
@ -195,12 +185,8 @@ local_label:
|
||||
dsrlv $2, $4, 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
dsrlv $32, $32, $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
|
||||
lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid register number
|
||||
lb $4, -2147483649($5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
|
||||
lb $4, 2147483648($5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
|
||||
lb $4, 8($32) # CHECK: :[[@LINE]]:18: error: invalid register number
|
||||
lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid register number
|
||||
lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
|
||||
lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
|
||||
lbu $4, 8($32) # CHECK: :[[@LINE]]:19: error: invalid register number
|
||||
ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
|
||||
ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
|
||||
|
||||
Loading…
Reference in New Issue
Block a user