1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00

[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()

llvm-svn: 355864
This commit is contained in:
Alex Bradbury 2019-03-11 20:43:29 +00:00
parent 2b90fade91
commit dd6e68f13e
2 changed files with 4 additions and 4 deletions

View File

@ -813,8 +813,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
F->insert(I, IfFalseMBB);
F->insert(I, TailMBB);
// Move all remaining instructions to TailMBB.
TailMBB->splice(TailMBB->begin(), HeadMBB,
std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end());
TailMBB->splice(TailMBB->begin(), HeadMBB, std::next(MI.getIterator()),
HeadMBB->end());
// Update machine-CFG edges by transferring all successors of the current
// block to the new block which will contain the Phi node for the select.
TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);

View File

@ -382,8 +382,8 @@ unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
.addMBB(&DestBB, RISCVII::MO_LO);
RS->enterBasicBlockEnd(MBB);
unsigned Scav = RS->scavengeRegisterBackwards(
RISCV::GPRRegClass, MachineBasicBlock::iterator(LuiMI), false, 0);
unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
LuiMI.getIterator(), false, 0);
MRI.replaceRegWith(ScratchReg, Scav);
MRI.clearVirtRegs();
RS->setRegUsed(Scav);