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Also set addrmode6 alignment when align==size.

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Previously, we were only setting the alignment bits on over-aligned
loads and stores.

llvm-svn: 143160
This commit is contained in:
Jakob Stoklund Olesen 2011-10-27 22:39:16 +00:00
parent bd9c6b8914
commit de21509dcd
4 changed files with 16 additions and 6 deletions
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2
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -923,7 +923,7 @@ bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
// The maximum alignment is equal to the memory size being referenced.
unsigned LSNAlign = LSN->getAlignment();
unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
if (LSNAlign > MemSize && MemSize > 1)
if (LSNAlign >= MemSize && MemSize > 1)
Alignment = MemSize;
} else {
// All other uses of addrmode6 are for intrinsics. For now just record

4
test/CodeGen/ARM/vlddup.ll
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@ -32,7 +32,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind {
define <2 x float> @vld1dupf(float* %A) nounwind {
;CHECK: vld1dupf:
;CHECK: vld1.32 {d16[]}, [r0]
;CHECK: vld1.32 {d16[]}, [r0, :32]
%tmp0 = load float* %A
%tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
@ -51,7 +51,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
define <4 x float> @vld1dupQf(float* %A) nounwind {
;CHECK: vld1dupQf:
;CHECK: vld1.32 {d16[], d17[]}, [r0]
;CHECK: vld1.32 {d16[], d17[]}, [r0, :32]
%tmp0 = load float* %A
%tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer

14
test/CodeGen/ARM/vldlane.ll
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@ -31,9 +31,19 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
ret <2 x i32> %tmp3
}
define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
;CHECK: vld1lanei32a32:
;Check the alignment value. Legal values are none or :32.
;CHECK: vld1.32 {d16[1]}, [r0, :32]
%tmp1 = load <2 x i32>* %B
%tmp2 = load i32* %A, align 4
%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
ret <2 x i32> %tmp3
}
define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
;CHECK: vld1lanef:
;CHECK: vld1.32 {d16[1]}, [r0]
;CHECK: vld1.32 {d16[1]}, [r0, :32]
%tmp1 = load <2 x float>* %B
%tmp2 = load float* %A, align 4
%tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1
@ -69,7 +79,7 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
;CHECK: vld1laneQf:
;CHECK: vld1.32 {d16[0]}, [r0]
;CHECK: vld1.32 {d16[0]}, [r0, :32]
%tmp1 = load <4 x float>* %B
%tmp2 = load float* %A
%tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0

2
test/CodeGen/ARM/vstlane.ll
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@ -45,7 +45,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
;CHECK: vst1lanef:
;CHECK: vst1.32 {d16[1]}, [r0]
;CHECK: vst1.32 {d16[1]}, [r0, :32]
%tmp1 = load <2 x float>* %B
%tmp2 = extractelement <2 x float> %tmp1, i32 1
store float %tmp2, float* %A