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* Switch to new TmpInstruction model
* Switch to new MachineCodeForInstruction model llvm-svn: 1655
This commit is contained in:
Chris Lattner
parent
fe52dade08
commit
de742eb319
@ -16,6 +16,8 @@
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iMemory.h"
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@ -159,7 +161,7 @@ GetTmpForCC(Value* boolVal, const Method* method, const Type* ccType)
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// directly written to map using the ref returned by operator[].
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TmpInstruction*& tmpI = boolToTmpCache[boolVal];
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if (tmpI == NULL)
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tmpI = new TmpInstruction(TMP_INSTRUCTION_OPCODE, ccType, boolVal, NULL);
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tmpI = new TmpInstruction(ccType, boolVal);
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return tmpI;
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}
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@ -908,7 +910,7 @@ ForwardOperand(InstructionNode* treeNode,
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InstructionNode* parentInstrNode = (InstructionNode*) parent;
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Instruction* userInstr = parentInstrNode->getInstruction();
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MachineCodeForVMInstr& mvec = userInstr->getMachineInstrVec();
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MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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MachineInstr* minstr = mvec[i];
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@ -973,7 +975,7 @@ CreateCopyInstructionsByType(const TargetMachine& target,
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vector<TmpInstruction*> tempVec;
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target.getInstrInfo().CreateCodeToLoadConst(src,dest,minstrVec,tempVec);
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for (unsigned i=0; i < tempVec.size(); i++)
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dest->getMachineInstrVec().addTempValue(tempVec[i]);
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MachineCodeForInstruction::get(dest).addTemp(tempVec[i]);
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}
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else
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{ // Create the appropriate add instruction.
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@ -1148,9 +1150,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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cast<ReturnInst>(subtreeRoot->getInstruction());
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assert(returnInstr->getOpcode() == Instruction::Ret);
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Instruction* returnReg = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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returnInstr, NULL);
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returnInstr->getMachineInstrVec().addTempValue(returnReg);
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Instruction* returnReg = new TmpInstruction(returnInstr);
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MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
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mvec[0] = new MachineInstr(JMPLRET);
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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@ -1391,9 +1392,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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const Type* destTypeToUse =
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(dest->getType() == Type::LongTy)? Type::DoubleTy
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: Type::FloatTy;
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destForCast = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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destTypeToUse, leftVal, NULL);
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dest->getMachineInstrVec().addTempValue(destForCast);
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destForCast = new TmpInstruction(destTypeToUse, leftVal);
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MachineCodeForInstruction &MCFI =
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MachineCodeForInstruction::get(dest);
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MCFI.addTemp(destForCast);
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vector<TmpInstruction*> tempVec;
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target.getInstrInfo().CreateCodeToCopyFloatToInt(
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@ -1402,7 +1404,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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minstrVec, tempVec, target);
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for (unsigned i=0; i < tempVec.size(); ++i)
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dest->getMachineInstrVec().addTempValue(tempVec[i]);
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MCFI.addTemp(tempVec[i]);
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}
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else
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destForCast = leftVal;
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@ -1434,7 +1436,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// so do the check here instead of only for ToFloatTy(reg).
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//
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if (subtreeRoot->parent() != NULL &&
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((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD)
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MachineCodeForInstruction::get(((InstructionNode*)subtreeRoot->parent())->getInstruction())[0]->getOpCode() == FSMULD)
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{
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numInstr = 0;
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forwardOperandNum = 0;
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@ -1468,9 +1470,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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(leftVal->getType() == Type::LongTy)? Type::DoubleTy
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: Type::FloatTy;
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srcForCast = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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srcTypeToUse, dest, NULL);
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dest->getMachineInstrVec().addTempValue(srcForCast);
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srcForCast = new TmpInstruction(srcTypeToUse, dest);
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MachineCodeForInstruction &DestMCFI =
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MachineCodeForInstruction::get(dest);
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DestMCFI.addTemp(srcForCast);
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vector<MachineInstr*> minstrVec;
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vector<TmpInstruction*> tempVec;
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@ -1483,7 +1486,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec[n++] = minstrVec[i];
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for (unsigned i=0; i < tempVec.size(); ++i)
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dest->getMachineInstrVec().addTempValue(tempVec[i]);
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DestMCFI.addTemp(tempVec[i]);
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}
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else
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srcForCast = leftVal;
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@ -1574,14 +1577,13 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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{
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Instruction* remInstr = subtreeRoot->getInstruction();
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TmpInstruction* quot = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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TmpInstruction* quot = new TmpInstruction(
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subtreeRoot->leftChild()->getValue(),
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subtreeRoot->rightChild()->getValue());
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TmpInstruction* prod = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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TmpInstruction* prod = new TmpInstruction(
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quot,
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subtreeRoot->rightChild()->getValue());
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remInstr->getMachineInstrVec().addTempValue(quot);
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remInstr->getMachineInstrVec().addTempValue(prod);
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MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
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mvec[0] = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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@ -1663,8 +1665,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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{
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InstructionNode* parent = (InstructionNode*) subtreeRoot->parent();
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assert(parent->getNodeType() == InstrTreeNode::NTInstructionNode);
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const vector<MachineInstr*>&
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minstrVec = parent->getInstruction()->getMachineInstrVec();
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const MachineCodeForInstruction &minstrVec =
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MachineCodeForInstruction::get(parent->getInstruction());
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MachineOpCode parentOpCode;
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if (parent->getInstruction()->getOpcode() == Instruction::Br &&
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(parentOpCode = minstrVec[0]->getOpCode()) >= BRZ &&
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@ -1722,7 +1724,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
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setCCInstr->getParent()->getParent(),
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isFPCompare? Type::FloatTy : Type::IntTy);
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setCCInstr->getMachineInstrVec().addTempValue(tmpForCC);
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MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
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if (! isFPCompare)
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{
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@ -1884,10 +1886,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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ignore));
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// Create a temporary value to hold `tmp'
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Instruction* tmpInstr = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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Instruction* tmpInstr = new TmpInstruction(
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subtreeRoot->leftChild()->getValue(),
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NULL /*could insert tsize here*/);
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subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr);
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MachineCodeForInstruction::get(subtreeRoot->getInstruction()).addTemp(tmpInstr);
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// Instruction 1: mul numElements, typeSize -> tmp
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mvec[0] = new MachineInstr(MULX);
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@ -1928,8 +1930,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
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Value *callee = callInstr->getCalledValue();
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Instruction* retAddrReg = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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callInstr, NULL);
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Instruction* retAddrReg = new TmpInstruction(callInstr);
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// Note temporary values in the machineInstrVec for the VM instr.
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//
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@ -1937,7 +1938,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// The result value must go in slot N. This is assumed
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// in register allocation.
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//
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callInstr->getMachineInstrVec().addTempValue(retAddrReg);
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MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
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// Generate the machine instruction and its operands.
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