From de78ccb013775d03a94b5f58c3e877f0bab2f1af Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 12 Oct 2010 23:18:08 +0000 Subject: [PATCH] Move the ARM so_imm encoding into a custom operand encoder and remove the explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367 --- lib/Target/ARM/ARMCodeEmitter.cpp | 2 ++ lib/Target/ARM/ARMInstrInfo.td | 9 +++++-- lib/Target/ARM/ARMMCCodeEmitter.cpp | 40 ++++++++++------------------- 3 files changed, 23 insertions(+), 28 deletions(-) diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index c5a77736877..a50872b06fc 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -166,6 +166,8 @@ namespace { // far along that this one can be eliminated entirely. unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) + const { return 0; } /// getMovi32Value - Return binary encoding of operand for movw/movt. If the /// machine operand requires relocation, record the relocation and return diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b21e26d9722..fe9094df05b 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -323,6 +323,7 @@ def so_reg : Operand, // reg reg imm // into so_imm instructions: the 8-bit immediate is the least significant bits // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. def so_imm : Operand, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> { + string EncoderMethod = "getSOImmOpValue"; let PrintMethod = "printSOImmOperand"; } @@ -477,9 +478,11 @@ multiclass AsI1_bin_irs opcod, string opc, [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> { bits<4> Rd; bits<4> Rn; + bits<12> imm; let Inst{25} = 1; let Inst{15-12} = Rd; let Inst{19-16} = Rn; + let Inst{11-0} = imm; } } def rr : AsI1, UnaryDP { +def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, + "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP { bits<4> Rd; + bits<12> imm; let Inst{25} = 1; let Inst{15-12} = Rd; let Inst{19-16} = 0b0000; + let Inst{11-0} = imm; } let isReMaterializable = 1, isAsCheapAsAMove = 1 in diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 12219317091..8bb8b2616c8 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -55,6 +55,20 @@ public: // '1' respectively. return MI.getOperand(Op).getReg() == ARM::CPSR; } + /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. + unsigned getSOImmOpValue(const MCInst &MI, unsigned Op) const { + unsigned SoImm = MI.getOperand(Op).getImm(); + int SoImmVal = ARM_AM::getSOImmVal(SoImm); + assert(SoImmVal != -1 && "Not a valid so_imm value!"); + + // Encode rotate_imm. + unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) + << ARMII::SoRotImmShift; + + // Encode immed_8. + Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); + return Binary; + } unsigned getNumFixupKinds() const { assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); @@ -93,19 +107,6 @@ public: } // end anonymous namespace -unsigned ARMMCCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) const { - int SoImmVal = ARM_AM::getSOImmVal(SoImm); - assert(SoImmVal != -1 && "Not a valid so_imm value!"); - - // Encode rotate_imm. - unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) - << ARMII::SoRotImmShift; - - // Encode immed_8. - Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); - return Binary; -} - MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM, MCContext &Ctx) { @@ -157,19 +158,6 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, unsigned Value = getBinaryCodeForInstr(MI); switch (Opcode) { default: break; - case ARM::MOVi: - // The shifted immediate value. - Value |= getMachineSoImmOpValue((unsigned)MI.getOperand(1).getImm()); - break; - case ARM::ADDri: - case ARM::ANDri: - case ARM::BICri: - case ARM::EORri: - case ARM::ORRri: - case ARM::SUBri: - // The shifted immediate value. - Value |= getMachineSoImmOpValue((unsigned)MI.getOperand(2).getImm()); - break; case ARM::ADDrs: case ARM::ANDrs: case ARM::BICrs: