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Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs"
This caused PR28387: Assertion "#operands for dag node doesn't match .td file!" llvm-svn: 274367
This commit is contained in:
Hans Wennborg
parent
5cfa5bd1e5
commit
dea5b2087b
@ -536,9 +536,9 @@ class T2FourReg<dag oops, dag iops, InstrItinClass itin,
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}
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class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
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string opc, list<dag> pattern>
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: T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
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opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern> {
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dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> RdLo;
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bits<4> RdHi;
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bits<4> Rn;
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@ -552,11 +552,10 @@ class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
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let Inst{7-4} = opc7_4;
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let Inst{3-0} = Rm;
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}
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class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
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: T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
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(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
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opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
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RegConstraint<"$RLo = $RdLo, $RHi = $RdHi"> {
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class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
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dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> RdLo;
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bits<4> RdHi;
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bits<4> Rn;
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@ -2545,183 +2544,367 @@ def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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let Inst{7-4} = 0b0000; // Multiply
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}
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class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
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: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
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Requires<[IsThumb2, UseMulOps]> {
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def t2MLA: T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"mla", "\t$Rd, $Rn, $Rm, $Ra",
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[(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
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Requires<[IsThumb2, UseMulOps]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b000;
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let Inst{7-4} = op7_4;
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let Inst{7-4} = 0b0000; // Multiply
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}
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def t2MLA : T2FourRegMLA<0b0000, "mla",
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[(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
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rGPR:$Ra))]>;
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def t2MLS: T2FourRegMLA<0b0001, "mls",
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[(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
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rGPR:$Rm)))]>;
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def t2MLS: T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"mls", "\t$Rd, $Rn, $Rm, $Ra",
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[(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
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Requires<[IsThumb2, UseMulOps]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b000;
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let Inst{7-4} = 0b0001; // Multiply and Subtract
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}
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// Extra precision multiplies with low / high results
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let hasSideEffects = 0 in {
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let isCommutable = 1 in {
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def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>;
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def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>;
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def t2SMULL : T2MulLong<0b000, 0b0000,
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(outs rGPR:$RdLo, rGPR:$RdHi),
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(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
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"smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
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def t2UMULL : T2MulLong<0b010, 0b0000,
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(outs rGPR:$RdLo, rGPR:$RdHi),
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(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
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"umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
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} // isCommutable
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// Multiply + accumulate
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def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
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def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
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def t2UMAAL : T2MulLong<0b110, 0b0110, "umaal", []>,
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Requires<[IsThumb2, HasDSP]>;
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def t2SMLAL : T2MlaLong<0b100, 0b0000,
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(outs rGPR:$RdLo, rGPR:$RdHi),
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(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
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"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
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RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
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def t2UMLAL : T2MlaLong<0b110, 0b0000,
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(outs rGPR:$RdLo, rGPR:$RdHi),
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(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
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"umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
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RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
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def t2UMAAL : T2MulLong<0b110, 0b0110,
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(outs rGPR:$RdLo, rGPR:$RdHi),
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(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
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"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
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RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
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Requires<[IsThumb2, HasDSP]>;
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} // hasSideEffects
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// Rounding variants of the below included for disassembly only
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// Most significant word multiply
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class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
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: T2ThreeReg<(outs rGPR:$Rd),
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(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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opc, "\t$Rd, $Rn, $Rm", pattern>,
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Requires<[IsThumb2, HasDSP]> {
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def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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"smmul", "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b101;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-4} = op7_4;
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let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
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}
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def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
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rGPR:$Rm))]>;
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def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
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class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
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list<dag> pattern>
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: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
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def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
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"smmulr", "\t$Rd, $Rn, $Rm", []>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b101;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
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}
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def t2SMMLA : T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmla", "\t$Rd, $Rn, $Rm, $Ra",
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[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
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Requires<[IsThumb2, HasDSP, UseMulOps]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = op22_20;
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let Inst{7-4} = op7_4;
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let Inst{22-20} = 0b101;
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let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
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}
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def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
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[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
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def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
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def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
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[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
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def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
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def t2SMMLAR: T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b101;
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let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
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}
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class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
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list<dag> pattern>
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: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
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"\t$Rd, $Rn, $Rm", pattern>,
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Requires<[IsThumb2, HasDSP]> {
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def t2SMMLS: T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmls", "\t$Rd, $Rn, $Rm, $Ra",
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[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
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Requires<[IsThumb2, HasDSP, UseMulOps]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b110;
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let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
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}
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def t2SMMLSR:T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
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"smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b110;
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let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
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}
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multiclass T2I_smul<string opc, SDNode opnode> {
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def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
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(sext_inreg rGPR:$Rm, i16)))]>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = op22_20;
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let Inst{22-20} = 0b001;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-6} = 0b00;
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let Inst{5-4} = op5_4;
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let Inst{5-4} = 0b00;
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}
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def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
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(sra rGPR:$Rm, (i32 16))))]>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-6} = 0b00;
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let Inst{5-4} = 0b01;
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}
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def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
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(sext_inreg rGPR:$Rm, i16)))]>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-6} = 0b00;
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let Inst{5-4} = 0b10;
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}
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def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
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(sra rGPR:$Rm, (i32 16))))]>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-6} = 0b00;
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let Inst{5-4} = 0b11;
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}
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def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
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[]>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-6} = 0b00;
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let Inst{5-4} = 0b00;
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}
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def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
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!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
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[]>,
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Requires<[IsThumb2, HasDSP]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
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let Inst{7-6} = 0b00;
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let Inst{5-4} = 0b01;
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}
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}
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def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
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[(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
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(sext_inreg rGPR:$Rm, i16)))]>;
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def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
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[(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
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(sra rGPR:$Rm, (i32 16))))]>;
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def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
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[(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
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(sext_inreg rGPR:$Rm, i16)))]>;
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def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
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[(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
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(sra rGPR:$Rm, (i32 16))))]>;
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def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
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def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
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class T2FourRegSMLA<bits<2> op5_4, string opc, list<dag> pattern>
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: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
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opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
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Requires<[IsThumb2, HasDSP, UseMulOps]> {
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multiclass T2I_smla<string opc, SDNode opnode> {
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def BB : T2FourReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
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!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
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||||
[(set rGPR:$Rd, (add rGPR:$Ra,
|
||||
(opnode (sext_inreg rGPR:$Rn, i16),
|
||||
(sext_inreg rGPR:$Rm, i16))))]>,
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
let Inst{7-6} = 0b00;
|
||||
let Inst{5-4} = op5_4;
|
||||
let Inst{5-4} = 0b00;
|
||||
}
|
||||
|
||||
def BT : T2FourReg<
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
|
||||
(sra rGPR:$Rm, (i32 16)))))]>,
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
let Inst{7-6} = 0b00;
|
||||
let Inst{5-4} = 0b01;
|
||||
}
|
||||
|
||||
def TB : T2FourReg<
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sext_inreg rGPR:$Rm, i16))))]>,
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
let Inst{7-6} = 0b00;
|
||||
let Inst{5-4} = 0b10;
|
||||
}
|
||||
|
||||
def TT : T2FourReg<
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
|
||||
(sra rGPR:$Rm, (i32 16)))))]>,
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b001;
|
||||
let Inst{7-6} = 0b00;
|
||||
let Inst{5-4} = 0b11;
|
||||
}
|
||||
|
||||
def WB : T2FourReg<
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[]>,
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
let Inst{7-6} = 0b00;
|
||||
let Inst{5-4} = 0b00;
|
||||
}
|
||||
|
||||
def WT : T2FourReg<
|
||||
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
|
||||
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[]>,
|
||||
Requires<[IsThumb2, HasDSP, UseMulOps]> {
|
||||
let Inst{31-27} = 0b11111;
|
||||
let Inst{26-23} = 0b0110;
|
||||
let Inst{22-20} = 0b011;
|
||||
let Inst{7-6} = 0b00;
|
||||
let Inst{5-4} = 0b01;
|
||||
}
|
||||
}
|
||||
|
||||
def t2SMLABB : T2FourRegSMLA<0b00, "smlabb",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra,
|
||||
(mul (sext_inreg rGPR:$Rn, i16),
|
||||
(sext_inreg rGPR:$Rm, i16))))]>;
|
||||
def t2SMLABT : T2FourRegSMLA<0b01, "smlabt",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
|
||||
(sra rGPR:$Rm, (i32 16)))))]>;
|
||||
def t2SMLATB : T2FourRegSMLA<0b10, "smlatb",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
|
||||
(sext_inreg rGPR:$Rm, i16))))]>;
|
||||
def t2SMLATT : T2FourRegSMLA<0b11, "smlatt",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
|
||||
(sra rGPR:$Rm, (i32 16)))))]>;
|
||||
def t2SMLAWB : T2FourRegSMLA<0b00, "smlawb", []> {
|
||||
let Inst{22-20} = 0b011;
|
||||
}
|
||||
def t2SMLAWT : T2FourRegSMLA<0b01, "smlawt", []> {
|
||||
let Inst{22-20} = 0b011;
|
||||
}
|
||||
|
||||
class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern>
|
||||
: T2FourReg_mac<1, op22_20, op7_4,
|
||||
(outs rGPR:$Ra, rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
defm t2SMUL : T2I_smul<"smul", mul>;
|
||||
defm t2SMLA : T2I_smla<"smla", mul>;
|
||||
|
||||
// Halfword multiple accumulate long: SMLAL<x><y>
|
||||
def t2SMLALBB : T2SMLAL<0b100, 0b1000, "smlalbb", []>;
|
||||
def t2SMLALBT : T2SMLAL<0b100, 0b1001, "smlalbt", []>;
|
||||
def t2SMLALTB : T2SMLAL<0b100, 0b1010, "smlaltb", []>;
|
||||
def t2SMLALTT : T2SMLAL<0b100, 0b1011, "smlaltt", []>;
|
||||
|
||||
class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc>
|
||||
: T2ThreeReg_mac<0, op22_20, op7_4,
|
||||
(outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
|
||||
[/* For disassembly only; pattern left blank */]>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
|
||||
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
|
||||
def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">;
|
||||
def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">;
|
||||
def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">;
|
||||
def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">;
|
||||
|
||||
class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc>
|
||||
: T2FourReg_mac<0, op22_20, op7_4,
|
||||
(outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
|
||||
IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
|
||||
def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad">;
|
||||
def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx">;
|
||||
def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">;
|
||||
def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">;
|
||||
|
||||
class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
|
||||
: T2FourReg_mac<1, op22_20, op7_4,
|
||||
(outs rGPR:$Ra, rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
|
||||
def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
|
||||
def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
|
||||
def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
|
||||
def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
|
||||
def t2SMUAD: T2ThreeReg_mac<
|
||||
0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUADX:T2ThreeReg_mac<
|
||||
0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUSD: T2ThreeReg_mac<
|
||||
0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMUSDX:T2ThreeReg_mac<
|
||||
0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]> {
|
||||
let Inst{15-12} = 0b1111;
|
||||
}
|
||||
def t2SMLAD : T2FourReg_mac<
|
||||
0, 0b010, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLADX : T2FourReg_mac<
|
||||
0, 0b010, 0b0001, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
|
||||
"\t$Rd, $Rn, $Rm, $Ra", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
|
||||
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
|
||||
"\t$Ra, $Rd, $Rn, $Rm", []>,
|
||||
Requires<[IsThumb2, HasDSP]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Division Instructions.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user