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Shrink interval after moving copy in removePartialRedundancy
llvm-svn: 334963
This commit is contained in:
Krzysztof Parzyszek
parent
f6e62b21be
commit
deaab0b105
@ -1050,6 +1050,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
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BValNo->markUnused();
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LIS->extendToIndices(SR, EndPoints);
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}
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// If any dead defs were extended, truncate them.
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shrinkToUses(&IntB);
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// Finally, update the live-range of IntA.
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shrinkToUses(&IntA);
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239
test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
Normal file
239
test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
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@ -0,0 +1,239 @@
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# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s
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# REQUIRES: asserts
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#
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# This test will provoke a Couldn't join subrange unreachable without the
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# fix for http://llvm.org/PR35373
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#
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# GCN: S_CBRANCH_SCC1 %bb.6, implicit undef $scc
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--- |
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define amdgpu_ps void @regcoal-subrange-join-seg() local_unnamed_addr #0 {
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ret void
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}
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...
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---
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name: regcoal-subrange-join-seg
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_128 }
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- { id: 1, class: sreg_128 }
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- { id: 2, class: sreg_128 }
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- { id: 3, class: sreg_128 }
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- { id: 4, class: sreg_128 }
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- { id: 5, class: sreg_128 }
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- { id: 6, class: sreg_128 }
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- { id: 7, class: sreg_128 }
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- { id: 8, class: sreg_128 }
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- { id: 9, class: sreg_32_xm0 }
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- { id: 10, class: sreg_32_xm0 }
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- { id: 11, class: vgpr_32 }
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- { id: 12, class: vgpr_32 }
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- { id: 13, class: vgpr_32 }
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- { id: 14, class: sreg_32_xm0_xexec }
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- { id: 15, class: sreg_128 }
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- { id: 16, class: sreg_32 }
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- { id: 17, class: sreg_32_xm0 }
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- { id: 18, class: sreg_32_xm0 }
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- { id: 19, class: sreg_32_xm0 }
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- { id: 20, class: sreg_32_xm0 }
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- { id: 21, class: sreg_32_xm0_xexec }
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- { id: 22, class: sreg_128 }
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- { id: 23, class: sreg_32_xm0 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: sreg_64_xexec }
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- { id: 26, class: vgpr_32 }
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- { id: 27, class: sreg_32_xm0 }
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- { id: 28, class: sreg_32 }
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- { id: 29, class: sreg_128 }
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- { id: 30, class: sreg_32_xm0 }
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- { id: 31, class: sreg_32_xm0 }
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- { id: 32, class: vgpr_32 }
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- { id: 33, class: vgpr_32 }
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- { id: 34, class: vgpr_32 }
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- { id: 35, class: vgpr_32 }
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- { id: 36, class: vgpr_32 }
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- { id: 37, class: vgpr_32 }
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- { id: 38, class: vgpr_32 }
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- { id: 39, class: vgpr_32 }
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- { id: 40, class: vgpr_32 }
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- { id: 41, class: vgpr_32 }
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- { id: 42, class: vgpr_32 }
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- { id: 43, class: vgpr_32 }
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- { id: 44, class: vgpr_32 }
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- { id: 45, class: vgpr_32 }
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- { id: 46, class: vgpr_32 }
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- { id: 47, class: vgpr_32 }
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- { id: 48, class: vgpr_32 }
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- { id: 49, class: vreg_128 }
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- { id: 50, class: vreg_128 }
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- { id: 51, class: vreg_128 }
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- { id: 52, class: vreg_128 }
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- { id: 53, class: vreg_128 }
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- { id: 54, class: vreg_128 }
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- { id: 55, class: vgpr_32 }
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- { id: 56, class: vreg_128 }
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- { id: 57, class: vreg_128 }
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- { id: 58, class: vreg_128 }
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- { id: 59, class: vreg_128 }
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- { id: 60, class: vreg_128 }
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- { id: 61, class: vreg_128 }
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- { id: 62, class: vreg_128 }
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- { id: 63, class: vreg_128 }
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body: |
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bb.0:
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S_CBRANCH_SCC1 %bb.6, implicit undef $scc
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S_BRANCH %bb.1
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bb.1:
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S_CBRANCH_SCC1 %bb.4, implicit undef $scc
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S_BRANCH %bb.2
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bb.2:
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S_CBRANCH_SCC1 %bb.4, implicit undef $scc
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S_BRANCH %bb.3
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bb.3:
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bb.4:
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successors: %bb.5, %bb.6
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S_CBRANCH_SCC1 %bb.6, implicit undef $scc
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S_BRANCH %bb.5
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bb.5:
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bb.6:
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S_CBRANCH_SCC1 %bb.14, implicit undef $scc
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S_BRANCH %bb.7
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bb.7:
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S_CBRANCH_SCC1 %bb.9, implicit undef $scc
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S_BRANCH %bb.8
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bb.8:
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bb.9:
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successors: %bb.10, %bb.13
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S_CBRANCH_SCC1 %bb.13, implicit undef $scc
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S_BRANCH %bb.10
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bb.10:
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S_CBRANCH_SCC1 %bb.12, implicit undef $scc
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S_BRANCH %bb.11
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bb.11:
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bb.12:
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bb.13:
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bb.14:
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S_CBRANCH_SCC1 %bb.26, implicit undef $scc
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S_BRANCH %bb.15
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bb.15:
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S_CBRANCH_SCC1 %bb.20, implicit undef $scc
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S_BRANCH %bb.16
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bb.16:
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successors: %bb.17, %bb.19
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S_CBRANCH_SCC1 %bb.19, implicit undef $scc
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S_BRANCH %bb.17
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bb.17:
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successors: %bb.18, %bb.19
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S_CBRANCH_SCC1 %bb.19, implicit undef $scc
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S_BRANCH %bb.18
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bb.18:
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bb.19:
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bb.20:
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S_CBRANCH_SCC1 %bb.25, implicit undef $scc
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S_BRANCH %bb.21
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bb.21:
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successors: %bb.22, %bb.24
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S_CBRANCH_SCC1 %bb.24, implicit undef $scc
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S_BRANCH %bb.22
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bb.22:
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successors: %bb.23, %bb.24
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S_CBRANCH_SCC1 %bb.24, implicit undef $scc
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S_BRANCH %bb.23
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bb.23:
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bb.24:
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bb.25:
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bb.26:
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S_CBRANCH_SCC1 %bb.35, implicit undef $scc
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S_BRANCH %bb.27
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bb.27:
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S_CBRANCH_SCC1 %bb.32, implicit undef $scc
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S_BRANCH %bb.28
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bb.28:
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%9 = S_FF1_I32_B32 undef %10
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%13 = V_MAD_U32_U24 killed %9, 48, 32, 0, implicit $exec
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%45 = BUFFER_LOAD_DWORD_OFFEN killed %13, undef %15, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
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%46 = V_AND_B32_e32 1, killed %45, implicit $exec
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%21 = S_BUFFER_LOAD_DWORD_SGPR undef %22, undef %23, 0 :: (dereferenceable invariant load 4)
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%25 = V_CMP_GE_F32_e64 0, 0, 0, killed %21, 0, implicit $exec
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%26 = V_CNDMASK_B32_e64 0, -1, killed %25, implicit $exec
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%62 = IMPLICIT_DEF
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bb.29:
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successors: %bb.30(0x30000000), %bb.36(0x50000000)
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%53 = COPY killed %62
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%47 = V_ADD_I32_e32 -1, %46, implicit-def dead $vcc, implicit $exec
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%48 = V_OR_B32_e32 killed %47, %26, implicit $exec
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%49 = COPY %53
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%49.sub2 = COPY undef %48
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%51 = COPY killed %49
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%51.sub3 = COPY undef %26
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V_CMP_NE_U32_e32 0, killed %48, implicit-def $vcc, implicit $exec
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCZ %bb.30, implicit killed $vcc
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bb.36:
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%63 = COPY killed %51
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S_BRANCH %bb.31
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bb.30:
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%33 = V_MAD_F32 1, killed %53.sub0, 0, undef %34, 0, 0, 0, 0, implicit $exec
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%35 = V_MAC_F32_e32 killed %33, undef %36, undef %35, implicit $exec
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%38 = V_MAX_F32_e32 0, killed %35, implicit $exec
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%39 = V_LOG_F32_e32 killed %38, implicit $exec
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%40 = V_MUL_F32_e32 killed %39, undef %41, implicit $exec
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%42 = V_EXP_F32_e32 killed %40, implicit $exec
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dead %43 = V_MUL_F32_e32 killed %42, undef %44, implicit $exec
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%63 = COPY killed %51
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bb.31:
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%52 = COPY killed %63
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%62 = COPY killed %52
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S_BRANCH %bb.29
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bb.32:
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S_CBRANCH_SCC1 %bb.34, implicit undef $scc
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S_BRANCH %bb.33
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bb.33:
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bb.34:
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bb.35:
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S_ENDPGM
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...
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