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[FPEnv][AArch64] Implement lowering of llvm.set.rounding
Differential Revision: https://reviews.llvm.org/D96836
This commit is contained in:
Serge Pavlov
parent
04856db5a7
commit
dece4f91fe
@ -675,10 +675,13 @@ def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
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let TargetPrefix = "aarch64" in {
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class FPCR_Get_Intrinsic
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: DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrHasSideEffects]>;
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class FPCR_Set_Intrinsic
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: DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>;
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}
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// FPCR
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def int_aarch64_get_fpcr : FPCR_Get_Intrinsic;
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def int_aarch64_set_fpcr : FPCR_Set_Intrinsic;
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let TargetPrefix = "aarch64" in {
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class Crypto_AES_DataKey_Intrinsic
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@ -693,6 +693,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
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setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
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setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
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@ -3455,6 +3456,50 @@ SDValue AArch64TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
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return DAG.getMergeValues({AND, Chain}, dl);
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}
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SDValue AArch64TargetLowering::LowerSET_ROUNDING(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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SDValue Chain = Op->getOperand(0);
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SDValue RMValue = Op->getOperand(1);
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// The rounding mode is in bits 23:22 of the FPCR.
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// The llvm.set.rounding argument value to the rounding mode in FPCR mapping
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// is 0->3, 1->0, 2->1, 3->2. The formula we use to implement this is
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// ((arg - 1) & 3) << 22).
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//
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// The argument of llvm.set.rounding must be within the segment [0, 3], so
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// NearestTiesToAway (4) is not handled here. It is responsibility of the code
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// generated llvm.set.rounding to ensure this condition.
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// Calculate new value of FPCR[23:22].
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RMValue = DAG.getNode(ISD::SUB, DL, MVT::i32, RMValue,
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DAG.getConstant(1, DL, MVT::i32));
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RMValue = DAG.getNode(ISD::AND, DL, MVT::i32, RMValue,
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DAG.getConstant(0x3, DL, MVT::i32));
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RMValue =
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DAG.getNode(ISD::SHL, DL, MVT::i32, RMValue,
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DAG.getConstant(AArch64::RoundingBitsPos, DL, MVT::i32));
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RMValue = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, RMValue);
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// Get current value of FPCR.
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SDValue Ops[] = {
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Chain, DAG.getTargetConstant(Intrinsic::aarch64_get_fpcr, DL, MVT::i64)};
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SDValue FPCR =
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DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i64, MVT::Other}, Ops);
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Chain = FPCR.getValue(1);
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FPCR = FPCR.getValue(0);
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// Put new rounding mode into FPSCR[23:22].
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const int RMMask = ~(AArch64::Rounding::rmMask << AArch64::RoundingBitsPos);
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FPCR = DAG.getNode(ISD::AND, DL, MVT::i64, FPCR,
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DAG.getConstant(RMMask, DL, MVT::i64));
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FPCR = DAG.getNode(ISD::OR, DL, MVT::i64, FPCR, RMValue);
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SDValue Ops2[] = {
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Chain, DAG.getTargetConstant(Intrinsic::aarch64_set_fpcr, DL, MVT::i64),
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FPCR};
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return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2);
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}
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SDValue AArch64TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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@ -4378,6 +4423,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
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return LowerFSINCOS(Op, DAG);
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case ISD::FLT_ROUNDS_:
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return LowerFLT_ROUNDS_(Op, DAG);
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case ISD::SET_ROUNDING:
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return LowerSET_ROUNDING(Op, DAG);
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case ISD::MUL:
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return LowerMUL(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN:
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@ -449,6 +449,21 @@ static inline bool isDef32(const SDNode &N) {
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} // end anonymous namespace
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namespace AArch64 {
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/// Possible values of current rounding mode, which is specified in bits
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/// 23:22 of FPCR.
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enum Rounding {
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RN = 0, // Round to Nearest
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RP = 1, // Round towards Plus infinity
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RM = 2, // Round towards Minus infinity
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RZ = 3, // Round towards Zero
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rmMask = 3 // Bit mask selecting rounding mode
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};
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// Bit position of rounding mode bits in FPCR.
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const unsigned RoundingBitsPos = 22;
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} // namespace AArch64
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class AArch64Subtarget;
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class AArch64TargetMachine;
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@ -898,6 +913,7 @@ private:
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SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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@ -1247,6 +1247,7 @@ def : Pat<(readcyclecounter), (MRS 0xdce8)>;
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// FPCR register
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def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>;
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def : Pat<(int_aarch64_set_fpcr i64:$val), (MSR 0xda20, GPR64:$val)>;
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// Generic system instructions
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def SYSxt : SystemXtI<0, "sys">;
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70
test/CodeGen/AArch64/fpenv.ll
Normal file
70
test/CodeGen/AArch64/fpenv.ll
Normal file
@ -0,0 +1,70 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s
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define void @func_02(i32 %rm) {
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call void @llvm.set.rounding(i32 %rm)
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ret void
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}
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; CHECK-LABEL: func_02:
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; CHECK: sub w9, w0, #1
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; CHECK: mrs x8, FPCR
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; CHECK: and w9, w9, #0x3
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; CHECK: and x8, x8, #0xffffffffff3fffff
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; CHECK: lsl w9, w9, #22
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; CHECK: orr x8, x8, x9
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; CHECK: msr FPCR, x8
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; CHECK: ret
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define void @func_03() {
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call void @llvm.set.rounding(i32 0)
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ret void
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}
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; CHECK-LABEL: func_03
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; CHECK: mrs x8, FPCR
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; CHECK: orr x8, x8, #0xc00000
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; CHECK: msr FPCR, x8
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; CHECK: ret
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define void @func_04() {
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call void @llvm.set.rounding(i32 1)
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ret void
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}
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; CHECK-LABEL: func_04
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; CHECK: mrs x8, FPCR
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; CHECK: and x8, x8, #0xffffffffff3fffff
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; CHECK: msr FPCR, x8
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; CHECK: ret
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define void @func_05() {
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call void @llvm.set.rounding(i32 2)
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ret void
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}
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; CHECK-LABEL: func_05
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; CHECK: mrs x8, FPCR
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; CHECK: and x8, x8, #0xffffffffff3fffff
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; CHECK: orr x8, x8, #0x400000
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; CHECK: msr FPCR, x8
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; CHECK: ret
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define void @func_06() {
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call void @llvm.set.rounding(i32 3)
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ret void
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}
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; CHECK-LABEL: func_06
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; CHECK: mrs x8, FPCR
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; CHECK: and x8, x8, #0xffffffffff3fffff
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; CHECK: orr x8, x8, #0x800000
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; CHECK: msr FPCR, x8
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; CHECK: ret
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declare void @llvm.set.rounding(i32)
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