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[RISCV] Reorder checks in RISCVTTIImpl::getGatherScatterOpCost to avoid calling getMinRVVVectorSizeInBits() when V extension is not enabled.

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getMinRVVVectorSizeInBits() asserts if the V extension isn't
enabled. So check that gather/scatter is legal first since it
already contains a check for V extension being enabled. It
also already checks getMinRVVVectorSizeInBits for fixed length
vectors so we don't need a check in getGatherScatterOpCost.
This commit is contained in:
Craig Topper 2021-03-25 14:20:38 -07:00
parent e73adcc6fa
commit deeab5c08f
3 changed files with 9 additions and 5 deletions
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10
lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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@ -148,11 +148,6 @@ unsigned RISCVTTIImpl::getGatherScatterOpCost(
return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
Alignment, CostKind, I); Alignment, CostKind, I);
// FIXME: Only supporting fixed vectors for now.
if (!isa<FixedVectorType>(DataTy) || ST->getMinRVVVectorSizeInBits() == 0)
return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
Alignment, CostKind, I);
if ((Opcode == Instruction::Load && if ((Opcode == Instruction::Load &&
!isLegalMaskedGather(DataTy, Align(Alignment))) || !isLegalMaskedGather(DataTy, Align(Alignment))) ||
(Opcode == Instruction::Store && (Opcode == Instruction::Store &&
@ -160,6 +155,11 @@ unsigned RISCVTTIImpl::getGatherScatterOpCost(
return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
Alignment, CostKind, I); Alignment, CostKind, I);
// FIXME: Only supporting fixed vectors for now.
if (!isa<FixedVectorType>(DataTy))
return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
Alignment, CostKind, I);
auto *VTy = cast<FixedVectorType>(DataTy); auto *VTy = cast<FixedVectorType>(DataTy);
unsigned NumLoads = VTy->getNumElements(); unsigned NumLoads = VTy->getNumElements();
unsigned MemOpCost = unsigned MemOpCost =

2
test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
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@ -1,5 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s ; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s
; Sanity check that we don't crash querying costs when vectors are not enabled.
; RUN: opt -cost-model -analyze -mtriple=riscv64
define i32 @masked_gather() { define i32 @masked_gather() {
; CHECK-LABEL: 'masked_gather' ; CHECK-LABEL: 'masked_gather'

2
test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
View File

@ -1,5 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s ; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s
; Sanity check that we don't crash querying costs when vectors are not enabled.
; RUN: opt -cost-model -analyze -mtriple=riscv64
define i32 @masked_scatter() { define i32 @masked_scatter() {
; CHECK-LABEL: 'masked_scatter' ; CHECK-LABEL: 'masked_scatter'