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[mips][microMIPS] Implement SW and SWE instructions
Differential Revision: http://reviews.llvm.org/D10869 llvm-svn: 245293
This commit is contained in:
Zoran Jovanovic
parent
056f7ddc7b
commit
df033f686f
@ -951,6 +951,10 @@ public:
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template <unsigned Bits> bool isMemWithSimmOffset() const {
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return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
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}
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template <unsigned Bits> bool isMemWithSimmOffsetGPR() const {
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return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
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&& getMemBase()->isGPRAsmReg();
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}
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bool isMemWithGRPMM16Base() const {
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return isMem() && getMemBase()->isMM16AsmReg();
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}
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@ -284,6 +284,11 @@ static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -1304,6 +1309,24 @@ static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<9>(Insn & 0x1ff);
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unsigned Reg = fieldFromInstruction(Insn, 21, 5);
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unsigned Base = fieldFromInstruction(Insn, 16, 5);
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Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::createReg(Reg));
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Inst.addOperand(MCOperand::createReg(Base));
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Inst.addOperand(MCOperand::createImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -287,3 +287,33 @@ class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<in
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let Inst{10} = rotate;
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let Inst{9-0} = funct;
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}
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class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<21> addr;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = addr{20-16};
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let Inst{15-0} = addr{15-0};
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}
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class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
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bits<3> funct> : MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-12} = fmt;
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let Inst{11-9} = funct;
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let Inst{8-0} = offset;
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}
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@ -66,6 +66,8 @@ class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
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class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
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class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
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class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
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class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
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class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
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class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
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class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
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@ -108,6 +110,26 @@ class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
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list<Register> Defs = [RA];
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}
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//===----------------------------------------------------------------------===//
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//
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// Operand Definitions
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//
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//===----------------------------------------------------------------------===//
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def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
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let Name = "MemOffsetSimm9GPR";
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let SuperClasses = [MipsMemAsmOperand];
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
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}
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def mem_simm9gpr : mem_generic {
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let MIOperandInfo = (ops ptr_rc, simm9);
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let EncoderMethod = "getMemEncoding";
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let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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@ -277,6 +299,18 @@ class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
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class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
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class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
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class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
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SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary,
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ComplexPattern Addr = addr> :
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InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMem";
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let mayStore = 1;
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}
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class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
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class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -348,6 +382,12 @@ def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
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def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
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def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
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def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
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let DecoderMethod = "DecodeMemMMImm16" in {
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def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
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}
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let DecoderMethod = "DecodeMemMMImm9" in {
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def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
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}
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}
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//===----------------------------------------------------------------------===//
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@ -112,3 +112,6 @@
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0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4
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0xf8,0xa6,0x00,0x04 # CHECK: sw $5, 4($6)
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0x60,0xa4,0xae,0x08 # CHECK: swe $5, 8($4)
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@ -4,3 +4,6 @@
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break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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swe $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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swe $5, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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swe $5, 512($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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@ -58,4 +58,6 @@
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subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
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xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
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xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
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sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
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swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
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