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[RISCV] Simplify vector instruction handling in RISCVMCInstLower.cpp.

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Use RegisterClass::contains instead of going through getMinimalPhysRegClass
and hasSuperClassEq.

Remove the special case for NoRegister. It's identical to the
handling for any other regsiter that isn't VRM2/M4/M8.
This commit is contained in:
Craig Topper 2020-12-10 13:37:42 -08:00
parent 23fb61a411
commit df0fb7b768
1 changed files with 3 additions and 11 deletions
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14
lib/Target/RISCV/RISCVMCInstLower.cpp
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@ -160,17 +160,9 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
case MachineOperand::MO_Register: {
unsigned Reg = MO.getReg();
// Nothing to do on NoRegister operands (used as vector mask operand on
// unmasked instructions)
if (Reg == RISCV::NoRegister) {
MCOp = MCOperand::createReg(Reg);
break;
}
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
if (RC->hasSuperClassEq(&RISCV::VRM2RegClass) ||
RC->hasSuperClassEq(&RISCV::VRM4RegClass) ||
RC->hasSuperClassEq(&RISCV::VRM8RegClass)) {
if (RISCV::VRM2RegClass.contains(Reg) ||
RISCV::VRM4RegClass.contains(Reg) ||
RISCV::VRM8RegClass.contains(Reg)) {
Reg = TRI->getSubReg(Reg, RISCV::sub_vrm2);
assert(Reg && "Subregister does not exist");
}