From dfcc535bbea4821ddaf7be9b638346ac2d167d54 Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Mon, 16 Sep 2013 23:29:03 +0000 Subject: [PATCH] Debug info: Fix PR16736 and rdar://problem/14990587. A DBG_VALUE is register-indirect iff the first operand is a register _and_ the second operand is an immediate. llvm-svn: 190821 --- include/llvm/CodeGen/MachineInstr.h | 7 +++ lib/CodeGen/InlineSpiller.cpp | 2 +- lib/CodeGen/LiveDebugVariables.cpp | 3 +- lib/CodeGen/RegAllocFast.cpp | 4 +- lib/CodeGen/SelectionDAG/FastISel.cpp | 1 + lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- test/DebugInfo/ARM/PR16736.ll | 63 +++++++++++++++++++ 7 files changed, 77 insertions(+), 5 deletions(-) create mode 100644 test/DebugInfo/ARM/PR16736.ll diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index e54c5c5174f..c67c729b77e 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -637,6 +637,13 @@ public: bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } + /// A DBG_VALUE is indirect iff the first operand is a register and + /// the second operand is an immediate. + bool isIndirectDebugValue() const { + return (getOpcode() == TargetOpcode::DBG_VALUE) + && getOperand(0).isReg() + && getOperand(1).isImm(); + } bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } bool isKill() const { return getOpcode() == TargetOpcode::KILL; } diff --git a/lib/CodeGen/InlineSpiller.cpp b/lib/CodeGen/InlineSpiller.cpp index d5f300f9aa2..13db5f44cb0 100644 --- a/lib/CodeGen/InlineSpiller.cpp +++ b/lib/CodeGen/InlineSpiller.cpp @@ -1191,7 +1191,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { // Debug values are not allowed to affect codegen. if (MI->isDebugValue()) { // Modify DBG_VALUE now that the value is in a spill slot. - bool IsIndirect = MI->getOperand(1).isImm(); + bool IsIndirect = MI->isIndirectDebugValue(); uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; const MDNode *MDPtr = MI->getOperand(2).getMetadata(); DebugLoc DL = MI->getDebugLoc(); diff --git a/lib/CodeGen/LiveDebugVariables.cpp b/lib/CodeGen/LiveDebugVariables.cpp index 12164450825..4b8395bae7d 100644 --- a/lib/CodeGen/LiveDebugVariables.cpp +++ b/lib/CodeGen/LiveDebugVariables.cpp @@ -457,9 +457,10 @@ bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) { } // Get or create the UserValue for (variable,offset). - bool IsIndirect = MI->getOperand(1).isImm(); + bool IsIndirect = MI->isIndirectDebugValue(); unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; const MDNode *Var = MI->getOperand(2).getMetadata(); + //here. UserValue *UV = getUserValue(Var, Offset, IsIndirect, MI->getDebugLoc()); UV->addDef(Idx, MI->getOperand(0)); return true; diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index 6617e50f7f9..400025074ca 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -298,7 +298,7 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) { MachineInstr *DBG = LRIDbgValues[li]; const MDNode *MDPtr = DBG->getOperand(2).getMetadata(); - bool IsIndirect = DBG->getOperand(1).isImm(); // Register-indirect value? + bool IsIndirect = DBG->isIndirectDebugValue(); uint64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0; DebugLoc DL; if (MI == MBB->end()) { @@ -856,7 +856,7 @@ void RAFast::AllocateBasicBlock() { } else { // Modify DBG_VALUE now that the value is in a spill slot. - bool IsIndirect = MI->getOperand(1).isImm(); + bool IsIndirect = MI->isIndirectDebugValue(); uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; const MDNode *MDPtr = MI->getOperand(MI->getNumOperands()-1).getMetadata(); diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index b4ac948fc11..b25e0317839 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -688,6 +688,7 @@ bool FastISel::SelectCall(const User *I) { .addFPImm(CF).addImm(DI->getOffset()) .addMetadata(DI->getVariable()); } else if (unsigned Reg = lookUpRegForValue(V)) { + // FIXME: This does not handle register-indirect values at offset 0. bool IsIndirect = DI->getOffset() != 0; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, IsIndirect, Reg, DI->getOffset(), DI->getVariable()); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 68367bbc67d..6066f50c74e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -422,7 +422,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { MachineBasicBlock::iterator InsertPos = Def; const MDNode *Variable = MI->getOperand(MI->getNumOperands()-1).getMetadata(); - bool IsIndirect = MI->getOperand(1).isImm(); + bool IsIndirect = MI->isIndirectDebugValue(); unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; // Def is never a terminator here, so it is ok to increment InsertPos. BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), diff --git a/test/DebugInfo/ARM/PR16736.ll b/test/DebugInfo/ARM/PR16736.ll new file mode 100644 index 00000000000..87619f97743 --- /dev/null +++ b/test/DebugInfo/ARM/PR16736.ll @@ -0,0 +1,63 @@ +; RUN: llc -filetype=asm < %s | FileCheck %s +; CHECK: @DEBUG_VALUE: h:x <- [R{{.*}}+{{.*}}] +; generated from: +; +; int f(); +; void g(float); +; void h(int, int, int, int, float x) { +; g(x = f()); +; } +; +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:32-n32-S64" +target triple = "thumbv7-apple-ios" + +; Function Attrs: nounwind +define arm_aapcscc void @_Z1hiiiif(i32, i32, i32, i32, float %x) #0 { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %0}, i64 0, metadata !12), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !13), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %2}, i64 0, metadata !14), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %3}, i64 0, metadata !15), !dbg !18 + tail call void @llvm.dbg.value(metadata !{float %x}, i64 0, metadata !16), !dbg !18 + %call = tail call arm_aapcscc i32 @_Z1fv() #3, !dbg !19 + %conv = sitofp i32 %call to float, !dbg !19 + tail call void @llvm.dbg.value(metadata !{float %conv}, i64 0, metadata !16), !dbg !19 + tail call arm_aapcscc void @_Z1gf(float %conv) #3, !dbg !19 + ret void, !dbg !20 +} + +declare arm_aapcscc void @_Z1gf(float) + +declare arm_aapcscc i32 @_Z1fv() + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata) #2 + +attributes #0 = { nounwind } +attributes #2 = { nounwind readnone } +attributes #3 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!17} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 (trunk 190804) (llvm/trunk 190797)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [//] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"/", metadata !""} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"h", metadata !"h", metadata !"_Z1hiiiif", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32, i32, i32, i32, float)* @_Z1hiiiif, null, null, metadata !11, i32 3} ; [ DW_TAG_subprogram ] [line 3] [def] [h] +!5 = metadata !{metadata !"/arm.cpp", metadata !""} +!6 = metadata !{i32 786473, metadata !5} ; [ DW_TAG_file_type ] [//arm.cpp] +!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{null, metadata !9, metadata !9, metadata !9, metadata !9, metadata !10} +!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!10 = metadata !{i32 786468, null, null, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float] +!11 = metadata !{metadata !12, metadata !13, metadata !14, metadata !15, metadata !16} +!12 = metadata !{i32 786689, metadata !4, metadata !"", metadata !6, i32 16777219, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [line 3] +!13 = metadata !{i32 786689, metadata !4, metadata !"", metadata !6, i32 33554435, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [line 3] +!14 = metadata !{i32 786689, metadata !4, metadata !"", metadata !6, i32 50331651, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [line 3] +!15 = metadata !{i32 786689, metadata !4, metadata !"", metadata !6, i32 67108867, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [line 3] +!16 = metadata !{i32 786689, metadata !4, metadata !"x", metadata !6, i32 83886083, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [x] [line 3] +!17 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!18 = metadata !{i32 3, i32 0, metadata !4, null} +!19 = metadata !{i32 4, i32 0, metadata !4, null} +!20 = metadata !{i32 5, i32 0, metadata !4, null}