From e0468ce3e170d111a019383973bb126cd0416a4a Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Sat, 13 Apr 2013 00:55:41 +0000 Subject: [PATCH] [mips] Reapply r179420 and r179421. llvm-svn: 179434 --- lib/Target/Mips/MipsDSPInstrInfo.td | 34 ++++++-- lib/Target/Mips/MipsInstrInfo.td | 11 ++- lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 + lib/Target/Mips/MipsSEISelLowering.cpp | 5 ++ test/CodeGen/Mips/dsp-patterns.ll | 113 +++++++++++++++++++++++-- 5 files changed, 147 insertions(+), 18 deletions(-) diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index 3c116e1264b..df8ba9db9d2 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -515,27 +515,27 @@ class INSV_DESC_BASE, IsCommutable; class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, NoItinerary, DSPRegs, DSPRegs>, IsCommutable; -class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary, +class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary, DSPRegs, DSPRegs>; class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, NoItinerary, DSPRegs, DSPRegs>; -class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary, +class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary, DSPRegs, DSPRegs>, IsCommutable; class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, NoItinerary, DSPRegs, DSPRegs>, IsCommutable; -class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary, +class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary, DSPRegs, DSPRegs>; class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, @@ -548,10 +548,10 @@ class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, NoItinerary, CPURegs, CPURegs>; -class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary, +class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary, CPURegs, CPURegs>, IsCommutable; -class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary, +class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary, CPURegs, CPURegs>, IsCommutable, UseDSPCtrl; @@ -951,7 +951,7 @@ class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPRegs>; // Multiplication -class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", int_mips_mul_ph, NoItinerary, +class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary, DSPRegs>, IsCommutable; class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph, @@ -1232,6 +1232,26 @@ def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a), def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a), (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; +// Binary operations. +class DSPBinPat : + DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>; + +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; +def : DSPBinPat; + // Extr patterns. class EXTR_W_TY1_R2_Pat : DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)), diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 3a82e817130..44e9fb8dcb5 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -179,6 +179,7 @@ def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, AssemblerPredicate<"FeatureMips32">; def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, AssemblerPredicate<"!FeatureMips16">; +def NotDSP : Predicate<"!Subtarget.hasDSP()">; class MipsPat : Pat { let Predicates = [HasStdEnc]; @@ -1128,10 +1129,12 @@ def : MipsPat<(i32 imm:$imm), // Carry MipsPatterns def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), (SUBu CPURegs:$lhs, CPURegs:$rhs)>; -def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), - (ADDu CPURegs:$lhs, CPURegs:$rhs)>; -def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), - (ADDiu CPURegs:$src, imm:$imm)>; +let Predicates = [HasStdEnc, NotDSP] in { + def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), + (ADDu CPURegs:$lhs, CPURegs:$rhs)>; + def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), + (ADDiu CPURegs:$src, imm:$imm)>; +} // Call def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index e0f5832d9ed..0114687addd 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -303,6 +303,8 @@ std::pair MipsSEDAGToDAGISel::selectNode(SDNode *Node) { } case ISD::ADDE: { + if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC. + break; SDValue InFlag = Node->getOperand(2); Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); return std::make_pair(true, Result); diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 805228b6bcc..70ba985f3ef 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -45,12 +45,17 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) setOperationAction(Opc, VecTys[i], Expand); + setOperationAction(ISD::ADD, VecTys[i], Legal); + setOperationAction(ISD::SUB, VecTys[i], Legal); setOperationAction(ISD::LOAD, VecTys[i], Legal); setOperationAction(ISD::STORE, VecTys[i], Legal); setOperationAction(ISD::BITCAST, VecTys[i], Legal); } } + if (Subtarget->hasDSPR2()) + setOperationAction(ISD::MUL, MVT::v2i16, Legal); + if (!TM.Options.UseSoftFloat) { addRegisterClass(MVT::f32, &Mips::FGR32RegClass); diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll index 0752f69c3e9..8fb86c23895 100644 --- a/test/CodeGen/Mips/dsp-patterns.ll +++ b/test/CodeGen/Mips/dsp-patterns.ll @@ -1,7 +1,8 @@ -; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s +; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1 +; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2 -; CHECK: test_lbux: -; CHECK: lbux ${{[0-9]+}} +; R1: test_lbux: +; R1: lbux ${{[0-9]+}} define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) { entry: @@ -10,8 +11,8 @@ entry: ret i8 %0 } -; CHECK: test_lhx: -; CHECK: lhx ${{[0-9]+}} +; R1: test_lhx: +; R1: lhx ${{[0-9]+}} define signext i16 @test_lhx(i16* nocapture %b, i32 %i) { entry: @@ -20,8 +21,8 @@ entry: ret i16 %0 } -; CHECK: test_lwx: -; CHECK: lwx ${{[0-9]+}} +; R1: test_lwx: +; R1: lwx ${{[0-9]+}} define i32 @test_lwx(i32* nocapture %b, i32 %i) { entry: @@ -29,3 +30,101 @@ entry: %0 = load i32* %add.ptr, align 4 ret i32 %0 } + +; R1: test_add_v2q15_: +; R1: addq.ph ${{[0-9]+}} + +define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %add = add <2 x i16> %0, %1 + %2 = bitcast <2 x i16> %add to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_sub_v2q15_: +; R1: subq.ph ${{[0-9]+}} + +define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %sub = sub <2 x i16> %0, %1 + %2 = bitcast <2 x i16> %sub to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R2: test_mul_v2q15_: +; R2: mul.ph ${{[0-9]+}} + +; mul.ph is an R2 instruction. Check that multiply node gets expanded. +; R1: test_mul_v2q15_: +; R1: mul ${{[0-9]+}} +; R1: mul ${{[0-9]+}} + +define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %mul = mul <2 x i16> %0, %1 + %2 = bitcast <2 x i16> %mul to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_add_v4i8_: +; R1: addu.qb ${{[0-9]+}} + +define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %1 = bitcast i32 %b.coerce to <4 x i8> + %add = add <4 x i8> %0, %1 + %2 = bitcast <4 x i8> %add to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_sub_v4i8_: +; R1: subu.qb ${{[0-9]+}} + +define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %1 = bitcast i32 %b.coerce to <4 x i8> + %sub = sub <4 x i8> %0, %1 + %2 = bitcast <4 x i8> %sub to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded. +; R2: test_mul_v4i8_: +; R2: mul ${{[0-9]+}} +; R2: mul ${{[0-9]+}} +; R2: mul ${{[0-9]+}} +; R2: mul ${{[0-9]+}} + +define { i32 } @test_mul_v4i8_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %1 = bitcast i32 %b.coerce to <4 x i8> + %mul = mul <4 x i8> %0, %1 + %2 = bitcast <4 x i8> %mul to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_addsc: +; R1: addsc ${{[0-9]+}} +; R1: addwc ${{[0-9]+}} + +define i64 @test_addsc(i64 %a, i64 %b) { +entry: + %add = add nsw i64 %b, %a + ret i64 %add +} +