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Revert "[GlobalISel] Add IRTranslator support for G_FFLOOR"
This reverts commit 8bbd570fd5205a04d88d2e5513a6e4adbd028039. Apparently adding ffloor breaks AMDGPU somehow, so I need to back this out while I look into it. llvm-svn: 353064
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@ -1077,11 +1077,6 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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return true;
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case Intrinsic::floor:
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MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR)
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.addDef(getOrCreateVReg(CI))
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.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
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return true;
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case Intrinsic::cos:
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MIRBuilder.buildInstr(TargetOpcode::G_FCOS)
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.addDef(getOrCreateVReg(CI))
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@ -2324,14 +2324,6 @@ define float @test_sqrt_f32(float %x) {
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ret float %y
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}
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declare float @llvm.floor.f32(float)
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define float @test_floor_f32(float %x) {
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; CHECK-LABEL: name: test_floor_f32
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; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}}
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%y = call float @llvm.floor.f32(float %x)
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ret float %y
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}
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; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32
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; CHECK: %1:_(s384) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load 48 from %ir.ptr, align 64)
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define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) {
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