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Revert "[GlobalISel] Add IRTranslator support for G_FFLOOR"

This reverts commit 8bbd570fd5205a04d88d2e5513a6e4adbd028039.

Apparently adding ffloor breaks AMDGPU somehow, so I need to back this out
while I look into it.

llvm-svn: 353064
This commit is contained in:
Jessica Paquette 2019-02-04 17:32:43 +00:00
parent 96bcfea5e8
commit e04ef6ecc0
2 changed files with 0 additions and 13 deletions

View File

@ -1077,11 +1077,6 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::floor:
MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::cos:
MIRBuilder.buildInstr(TargetOpcode::G_FCOS)
.addDef(getOrCreateVReg(CI))

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@ -2324,14 +2324,6 @@ define float @test_sqrt_f32(float %x) {
ret float %y
}
declare float @llvm.floor.f32(float)
define float @test_floor_f32(float %x) {
; CHECK-LABEL: name: test_floor_f32
; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}}
%y = call float @llvm.floor.f32(float %x)
ret float %y
}
; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32
; CHECK: %1:_(s384) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load 48 from %ir.ptr, align 64)
define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) {