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AMDGPU: Remove redundant combine

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This combine was already done in two places. The
generic combiner already has done this since
r217610, for adds (with a single use).

This one was added in r303641, and added support for handling
or as well. r313251 later added support to the generic
combine for or. It also turns out the isOrEquivalentToAdd
check is not necessary for this combine.

Additionally, we already reproduce this combine in yet
another place in the backend, although in that version
multiple uses of the add are still folded if it will
allow a fold into the addressing mode. That version needs
to be improved to understand ors though, as well as the
correct legal offsets for private.

llvm-svn: 317526
This commit is contained in:
Matt Arsenault 2017-11-07 00:06:32 +00:00
parent de7b7d7dae
commit e070357335
2 changed files with 0 additions and 39 deletions
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38
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
View File

@ -128,29 +128,6 @@ EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
} }
bool AMDGPUTargetLowering::isOrEquivalentToAdd(SelectionDAG &DAG, SDValue Op)
{
assert(Op.getOpcode() == ISD::OR);
SDValue N0 = Op->getOperand(0);
SDValue N1 = Op->getOperand(1);
EVT VT = N0.getValueType();
if (VT.isInteger() && !VT.isVector()) {
KnownBits LHSKnown, RHSKnown;
DAG.computeKnownBits(N0, LHSKnown);
if (LHSKnown.Zero.getBoolValue()) {
DAG.computeKnownBits(N1, RHSKnown);
if (!(~RHSKnown.Zero & ~LHSKnown.Zero))
return true;
}
}
return false;
}
unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
KnownBits Known; KnownBits Known;
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -2923,21 +2900,6 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
return DAG.getZExtOrTrunc(Shl, SL, VT); return DAG.getZExtOrTrunc(Shl, SL, VT);
} }
case ISD::OR:
if (!isOrEquivalentToAdd(DAG, LHS))
break;
LLVM_FALLTHROUGH;
case ISD::ADD: {
// shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1)
if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(LHS->getOperand(1))) {
SDValue Shl = DAG.getNode(ISD::SHL, SL, VT, LHS->getOperand(0),
SDValue(RHS, 0));
SDValue C2V = DAG.getConstant(C2->getAPIntValue() << RHSVal,
SDLoc(C2), VT);
return DAG.getNode(LHS->getOpcode(), SL, VT, Shl, C2V);
}
break;
}
} }
if (VT != MVT::i64) if (VT != MVT::i64)

1
lib/Target/AMDGPU/AMDGPUISelLowering.h
View File

@ -35,7 +35,6 @@ private:
SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const; SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
public: public:
static bool isOrEquivalentToAdd(SelectionDAG &DAG, SDValue Op);
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG); static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG); static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);