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Fix loop conditionals (MO.isDef() asserts that it's a reg) and
move some constraints around. llvm-svn: 111594
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@ -122,7 +122,8 @@ bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
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// Look to see if our OptionalDef is defining CPSR or CCR.
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// Look to see if our OptionalDef is defining CPSR or CCR.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isDef() && MO.isReg() && MO.getReg() == ARM::CPSR)
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if (!MO.isReg() || !MO.isDef()) continue;
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if (MO.getReg() == ARM::CPSR)
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*CPSR = true;
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*CPSR = true;
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}
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}
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return true;
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return true;
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