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CellSPU:
- Incorporate Tilmann Scheller's ISD::TRUNCATE custom lowering patch - Update SPU calling convention info, even if it's not used yet (but can be at some point or another) - Ensure that any-extended f32 loads are custom lowered, especially when they're promoted for use in printf. llvm-svn: 60438
This commit is contained in:
Scott Michel
parent
0834d959e9
commit
e0bbe7afb7
@ -21,6 +21,8 @@ class CCIfSubtarget<string F, CCAction A>
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// Return-value convention for Cell SPU: Everything can be passed back via $3:
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def RetCC_SPU : CallingConv<[
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CCIfType<[i8], CCAssignToReg<[R3]>>,
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CCIfType<[i16], CCAssignToReg<[R3]>>,
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CCIfType<[i32], CCAssignToReg<[R3]>>,
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CCIfType<[i64], CCAssignToReg<[R3]>>,
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CCIfType<[f32, f64], CCAssignToReg<[R3]>>,
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@ -30,30 +32,82 @@ def RetCC_SPU : CallingConv<[
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//===----------------------------------------------------------------------===//
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// CellSPU Argument Calling Conventions
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// FIXME
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// (note: this isn't used, but presumably should be at some point when other
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// targets do.)
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//===----------------------------------------------------------------------===//
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/*
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def CC_SPU : CallingConv<[
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// The first 8 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
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CCIfType<[i8], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i16], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[f64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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// SPU can pass back arguments in all
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CCIfType<[f32, f64], CCIfSubtarget<"isMachoABI()",
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CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>>,
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// Other sub-targets pass FP values in F1-10.
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8, F9,F10]>>,
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// The first 12 Vector arguments are passed in altivec registers.
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CCIfType<[v16i8, v8i16, v4i32, v4f32],
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
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/*
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToStack<16, 16>>*/
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CCAssignToStack<16, 16>>
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]>;
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*/
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*/
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@ -151,6 +151,8 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Custom);
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// SPU constant load actions are custom lowered:
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setOperationAction(ISD::Constant, MVT::i64, Custom);
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setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
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@ -277,6 +279,12 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::i64, Custom);
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// Custom lower truncates
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setOperationAction(ISD::TRUNCATE, MVT::i8, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::i32, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
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// SPU has a legal FP -> signed INT instruction
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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@ -2759,6 +2767,102 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(SPUISD::SELB, VT, trueval, falseval, compare);
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}
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//! Custom lower ISD::TRUNCATE
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static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
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{
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MVT VT = Op.getValueType();
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MVT::SimpleValueType simpleVT = VT.getSimpleVT();
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MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
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SDValue Op0 = Op.getOperand(0);
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MVT Op0VT = Op0.getValueType();
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MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
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SDValue PromoteScalar = DAG.getNode(SPUISD::PROMOTE_SCALAR, Op0VecVT, Op0);
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unsigned maskLow;
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unsigned maskHigh;
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// Create shuffle mask
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switch (Op0VT.getSimpleVT()) {
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case MVT::i128:
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switch (simpleVT) {
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case MVT::i64:
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// least significant doubleword of quadword
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maskHigh = 0x08090a0b;
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maskLow = 0x0c0d0e0f;
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break;
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case MVT::i32:
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// least significant word of quadword
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maskHigh = maskLow = 0x0c0d0e0f;
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break;
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case MVT::i16:
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// least significant halfword of quadword
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maskHigh = maskLow = 0x0e0f0e0f;
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break;
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case MVT::i8:
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// least significant byte of quadword
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maskHigh = maskLow = 0x0f0f0f0f;
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break;
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default:
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cerr << "Truncation to illegal type!";
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abort();
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}
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break;
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case MVT::i64:
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switch (simpleVT) {
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case MVT::i32:
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// least significant word of doubleword
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maskHigh = maskLow = 0x04050607;
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break;
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case MVT::i16:
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// least significant halfword of doubleword
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maskHigh = maskLow = 0x06070607;
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break;
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case MVT::i8:
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// least significant byte of doubleword
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maskHigh = maskLow = 0x07070707;
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break;
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default:
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cerr << "Truncation to illegal type!";
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abort();
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}
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break;
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case MVT::i32:
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case MVT::i16:
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switch (simpleVT) {
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case MVT::i16:
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// least significant halfword of word
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maskHigh = maskLow = 0x02030203;
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break;
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case MVT::i8:
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// least significant byte of word/halfword
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maskHigh = maskLow = 0x03030303;
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break;
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default:
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cerr << "Truncation to illegal type!";
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abort();
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}
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break;
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default:
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cerr << "Trying to lower truncation from illegal type!";
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abort();
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}
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// Use a shuffle to perform the truncation
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SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
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DAG.getConstant(maskHigh, MVT::i32),
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DAG.getConstant(maskLow, MVT::i32),
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DAG.getConstant(maskHigh, MVT::i32),
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DAG.getConstant(maskLow, MVT::i32));
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SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, Op0VecVT,
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PromoteScalar, PromoteScalar, shufMask);
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return DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
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DAG.getNode(ISD::BIT_CONVERT, VecVT, truncShuffle));
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}
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//! Custom (target-specific) lowering entry point
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/*!
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This is where LLVM's DAG selection process calls to do target-specific
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@ -2779,6 +2883,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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abort();
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}
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case ISD::LOAD:
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case ISD::EXTLOAD:
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case ISD::SEXTLOAD:
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case ISD::ZEXTLOAD:
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return LowerLOAD(Op, DAG, SPUTM.getSubtargetImpl());
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@ -2865,6 +2970,9 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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case ISD::SELECT_CC:
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return LowerSELECT_CC(Op, DAG);
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case ISD::TRUNCATE:
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return LowerTRUNCATE(Op, DAG);
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}
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return SDValue();
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@ -1371,13 +1371,6 @@ multiclass BitwiseOrByteImm
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defm ORBI : BitwiseOrByteImm;
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// Truncate i16 -> i8
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def ORBItrunc : ORBIInst<(outs R8C:$rT), (ins R16C:$rA, u10imm:$val),
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[/* empty */]>;
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def : Pat<(trunc R16C:$rSrc),
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(ORBItrunc R16C:$rSrc, 0)>;
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// OR halfword immediate
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class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
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RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
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@ -1403,13 +1396,6 @@ multiclass BitwiseOrHalfwordImm
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defm ORHI : BitwiseOrHalfwordImm;
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// Truncate i32 -> i16
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def ORHItrunc : ORHIInst<(outs R16C:$rT), (ins R32C:$rA, u10imm:$val),
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[/* empty */]>;
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def : Pat<(trunc R32C:$rSrc),
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(ORHItrunc R32C:$rSrc, 0)>;
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class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
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RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
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IntegerOp, pattern>;
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@ -1444,13 +1430,6 @@ multiclass BitwiseOrImm
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defm ORI : BitwiseOrImm;
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// Truncate i64 -> i32
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def ORItrunc : ORIInst<(outs R32C:$rT), (ins R64C:$rA, u10imm_i32:$val),
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[/* empty */]>;
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def : Pat<(trunc R64C:$rSrc),
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(ORItrunc R64C:$rSrc, 0)>;
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// ORX: "or" across the vector: or's $rA's word slots leaving the result in
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// $rT[0], slots 1-3 are zeroed.
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//
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@ -2014,13 +1993,6 @@ multiclass ShiftLeftQuadBytesImm
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defm SHLQBYI : ShiftLeftQuadBytesImm;
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// Special form for truncating i64 to i32:
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def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
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[/* no pattern, see below */]>;
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def : Pat<(trunc R64C:$rSrc),
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(SHLQBYItrunc64 R64C:$rSrc, 4)>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// Rotate halfword:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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81
test/CodeGen/CellSPU/trunc.ll
Normal file
81
test/CodeGen/CellSPU/trunc.ll
Normal file
@ -0,0 +1,81 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep shufb %t1.s | count 9
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; RUN: grep {ilhu.*1799} %t1.s | count 1
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; RUN: grep {ilhu.*771} %t1.s | count 3
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; RUN: grep {ilhu.*1543} %t1.s | count 1
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; RUN: grep {ilhu.*1029} %t1.s | count 1
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; RUN: grep {ilhu.*515} %t1.s | count 1
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; RUN: grep {iohl.*1799} %t1.s | count 1
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; RUN: grep {iohl.*771} %t1.s | count 3
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; RUN: grep {iohl.*1543} %t1.s | count 2
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; RUN: grep {iohl.*515} %t1.s | count 1
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; RUN: grep xsbh %t1.s | count 6
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; RUN: grep sfh %t1.s | count 5
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; ModuleID = 'trunc.bc'
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target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
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target triple = "spu"
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; codegen for i128 arguments is not implemented yet on CellSPU
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; once this changes uncomment the functions below
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; and update the expected results accordingly
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;define i8 @trunc_i128_i8(i128 %u) nounwind readnone {
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;entry:
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; %0 = trunc i128 %u to i8
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; ret i8 %0
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;}
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;define i16 @trunc_i128_i16(i128 %u) nounwind readnone {
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;entry:
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; %0 = trunc i128 %u to i16
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; ret i16 %0
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;}
|
||||
;define i32 @trunc_i128_i32(i128 %u) nounwind readnone {
|
||||
;entry:
|
||||
; %0 = trunc i128 %u to i32
|
||||
; ret i32 %0
|
||||
;}
|
||||
;define i64 @trunc_i128_i64(i128 %u) nounwind readnone {
|
||||
;entry:
|
||||
; %0 = trunc i128 %u to i64
|
||||
; ret i64 %0
|
||||
;}
|
||||
|
||||
define i8 @trunc_i64_i8(i64 %u, i8 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i8
|
||||
%1 = sub i8 %0, %v
|
||||
ret i8 %1
|
||||
}
|
||||
define i16 @trunc_i64_i16(i64 %u, i16 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i16
|
||||
%1 = sub i16 %0, %v
|
||||
ret i16 %1
|
||||
}
|
||||
define i32 @trunc_i64_i32(i64 %u, i32 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i64 %u to i32
|
||||
%1 = sub i32 %0, %v
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i8 @trunc_i32_i8(i32 %u, i8 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i32 %u to i8
|
||||
%1 = sub i8 %0, %v
|
||||
ret i8 %1
|
||||
}
|
||||
define i16 @trunc_i32_i16(i32 %u, i16 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i32 %u to i16
|
||||
%1 = sub i16 %0, %v
|
||||
ret i16 %1
|
||||
}
|
||||
|
||||
define i8 @trunc_i16_i8(i16 %u, i8 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = trunc i16 %u to i8
|
||||
%1 = sub i8 %0, %v
|
||||
ret i8 %1
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user