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Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values"
Rewrites test to use correct architecture triple; fixes incorrect reference in SourceLevelDebugging doc; simplifies `spillReg` behaviour so as to not be dependent on changes elsewhere in the patch stack. This reverts commit d2000b45d033c06dc7973f59909a0ad12887ff51.
This commit is contained in:
Stephen Tozer
parent
4a1dabde23
commit
e0cb677eb6
@ -5324,6 +5324,14 @@ The current supported opcode vocabulary is limited:
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``AsmPrinter`` pass when a call site parameter value
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(``DW_AT_call_site_parameter_value``) is represented as entry value
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of the parameter.
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- ``DW_OP_LLVM_arg, N`` is used in debug intrinsics that refer to more than one
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value, such as one that calculates the sum of two registers. This is always
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used in combination with an ordered list of values, such that
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``DW_OP_LLVM_arg, N`` refers to the ``N``th element in that list. For
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example, ``!DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_minus,
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DW_OP_stack_value)`` used with the list ``(%reg1, %reg2)`` would evaluate to
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``%reg1 - reg2``. This list of values should be provided by the containing
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intrinsic/instruction.
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- ``DW_OP_breg`` (or ``DW_OP_bregx``) represents a content on the provided
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signed offset of the specified register. The opcode is only generated by the
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``AsmPrinter`` pass to describe call site parameter value which requires an
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@ -576,13 +576,15 @@ the equivalent location is used.
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After MIR locations are assigned to each variable, machine pseudo-instructions
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corresponding to each ``llvm.dbg.value`` and ``llvm.dbg.addr`` intrinsic are
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inserted. These ``DBG_VALUE`` instructions appear thus:
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inserted. There are two forms of this type of instruction.
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The first form, ``DBG_VALUE``, appears thus:
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.. code-block:: text
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DBG_VALUE %1, $noreg, !123, !DIExpression()
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And have the following operands:
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And has the following operands:
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* The first operand can record the variable location as a register,
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a frame index, an immediate, or the base address register if the original
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debug intrinsic referred to memory. ``$noreg`` indicates the variable
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@ -594,6 +596,22 @@ And have the following operands:
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* Operand 3 is the Variable field of the original debug intrinsic.
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* Operand 4 is the Expression field of the original debug intrinsic.
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The second form, ``DBG_VALUE_LIST``, appears thus:
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.. code-block:: text
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DBG_VALUE_LIST !123, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus), %1, %2
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And has the following operands:
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* The first operand is the Variable field of the original debug intrinsic.
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* The second operand is the Expression field of the original debug intrinsic.
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* Any number of operands, from the 3rd onwards, record a sequence of variable
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location operands, which may take any of the same values as the first
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operand of the ``DBG_VALUE`` instruction above. These variable location
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operands are inserted into the final DWARF Expression in positions indicated
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by the DW_OP_LLVM_arg operator in the `DIExpression
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<LangRef.html#diexpression>`.
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The position at which the DBG_VALUEs are inserted should correspond to the
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positions of their matching ``llvm.dbg.value`` intrinsics in the IR block. As
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with optimization, LLVM aims to preserve the order in which variable
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@ -144,6 +144,7 @@ enum LocationAtom {
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DW_OP_LLVM_tag_offset = 0x1002, ///< Only used in LLVM metadata.
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DW_OP_LLVM_entry_value = 0x1003, ///< Only used in LLVM metadata.
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DW_OP_LLVM_implicit_pointer = 0x1004, ///< Only used in LLVM metadata.
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DW_OP_LLVM_arg = 0x1005, ///< Only used in LLVM metadata.
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};
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enum TypeKind : uint8_t {
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@ -420,11 +420,11 @@ public:
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/// instruction is indirect; will be an invalid register if this value is
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/// not indirect, and an immediate with value 0 otherwise.
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const MachineOperand &getDebugOffset() const {
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assert(isDebugValue() && "not a DBG_VALUE");
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assert(isNonListDebugValue() && "not a DBG_VALUE");
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return getOperand(1);
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}
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MachineOperand &getDebugOffset() {
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assert(isDebugValue() && "not a DBG_VALUE");
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assert(isNonListDebugValue() && "not a DBG_VALUE");
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return getOperand(1);
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}
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@ -439,6 +439,7 @@ public:
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/// Return the operand for the complex address expression referenced by
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/// this DBG_VALUE instruction.
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const MachineOperand &getDebugExpressionOp() const;
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MachineOperand &getDebugExpressionOp();
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/// Return the complex address expression referenced by
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@ -501,26 +502,43 @@ public:
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return *(debug_operands().begin() + Index);
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}
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/// Returns a pointer to the operand corresponding to a debug use of Reg, or
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/// nullptr if Reg is not used in any debug operand.
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const MachineOperand *getDebugOperandForReg(Register Reg) const {
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const MachineOperand *RegOp =
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find_if(debug_operands(), [Reg](const MachineOperand &Op) {
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/// Returns whether this debug value has at least one debug operand with the
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/// register \p Reg.
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bool hasDebugOperandForReg(Register Reg) const {
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return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
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return Op.isReg() && Op.getReg() == Reg;
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});
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return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
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}
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MachineOperand *getDebugOperandForReg(Register Reg) {
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MachineOperand *RegOp =
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find_if(debug_operands(), [Reg](const MachineOperand &Op) {
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return Op.isReg() && Op.getReg() == Reg;
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});
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return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
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/// Returns a range of all of the operands that correspond to a debug use of
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/// \p Reg.
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template <typename Operand, typename Instruction>
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static iterator_range<
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filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
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getDebugOperandsForReg(Instruction *MI, Register Reg) {
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std::function<bool(Operand & Op)> OpUsesReg(
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[Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
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return make_filter_range(MI->debug_operands(), OpUsesReg);
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}
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iterator_range<filter_iterator<const MachineOperand *,
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std::function<bool(const MachineOperand &Op)>>>
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getDebugOperandsForReg(Register Reg) const {
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return MachineInstr::getDebugOperandsForReg<const MachineOperand,
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const MachineInstr>(this, Reg);
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}
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iterator_range<filter_iterator<MachineOperand *,
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std::function<bool(MachineOperand &Op)>>>
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getDebugOperandsForReg(Register Reg) {
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return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
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this, Reg);
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}
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bool isDebugOperand(const MachineOperand *Op) const {
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return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
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}
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unsigned getDebugOperandIndex(const MachineOperand *Op) const {
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assert(Op >= adl_begin(debug_operands()) &&
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Op <= adl_end(debug_operands()) && "Expected a debug operand.");
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assert(isDebugOperand(Op) && "Expected a debug operand.");
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return std::distance(adl_begin(debug_operands()), Op);
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}
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@ -600,12 +618,16 @@ public:
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/// location for this DBG_VALUE instruction.
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iterator_range<mop_iterator> debug_operands() {
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assert(isDebugValue() && "Must be a debug value instruction.");
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return make_range(operands_begin(), operands_begin() + 1);
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return isDebugValueList()
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? make_range(operands_begin() + 2, operands_end())
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: make_range(operands_begin(), operands_begin() + 1);
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}
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/// \copydoc debug_operands()
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iterator_range<const_mop_iterator> debug_operands() const {
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assert(isDebugValue() && "Must be a debug value instruction.");
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return make_range(operands_begin(), operands_begin() + 1);
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return isDebugValueList()
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? make_range(operands_begin() + 2, operands_end())
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: make_range(operands_begin(), operands_begin() + 1);
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}
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/// Returns a range over all explicit operands that are register definitions.
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/// Implicit definition are not included!
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@ -1164,7 +1186,15 @@ public:
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// True if the instruction represents a position in the function.
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bool isPosition() const { return isLabel() || isCFIInstruction(); }
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bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
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bool isNonListDebugValue() const {
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return getOpcode() == TargetOpcode::DBG_VALUE;
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}
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bool isDebugValueList() const {
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return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
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}
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bool isDebugValue() const {
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return isNonListDebugValue() || isDebugValueList();
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}
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bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
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bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
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bool isDebugInstr() const {
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@ -1174,12 +1204,14 @@ public:
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return isDebugInstr() || isPseudoProbe();
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}
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bool isDebugOffsetImm() const { return getDebugOffset().isImm(); }
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bool isDebugOffsetImm() const {
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return isNonListDebugValue() && getDebugOffset().isImm();
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}
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/// A DBG_VALUE is indirect iff the location operand is a register and
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/// the offset operand is an immediate.
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bool isIndirectDebugValue() const {
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return isDebugValue() && getDebugOperand(0).isReg() && isDebugOffsetImm();
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return isDebugOffsetImm() && getDebugOperand(0).isReg();
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}
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/// A DBG_VALUE is an entry value iff its debug expression contains the
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@ -1189,8 +1221,13 @@ public:
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/// Return true if the instruction is a debug value which describes a part of
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/// a variable as unavailable.
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bool isUndefDebugValue() const {
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return isDebugValue() && getDebugOperand(0).isReg() &&
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!getDebugOperand(0).getReg().isValid();
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if (!isDebugValue())
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return false;
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// If any $noreg locations are given, this DV is undef.
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for (const MachineOperand &Op : debug_operands())
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if (Op.isReg() && !Op.getReg().isValid())
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return true;
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return false;
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}
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bool isPHI() const {
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@ -1265,6 +1302,7 @@ public:
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case TargetOpcode::EH_LABEL:
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case TargetOpcode::GC_LABEL:
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case TargetOpcode::DBG_VALUE:
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case TargetOpcode::DBG_VALUE_LIST:
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case TargetOpcode::DBG_INSTR_REF:
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case TargetOpcode::DBG_LABEL:
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case TargetOpcode::LIFETIME_START:
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@ -451,9 +451,16 @@ MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
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/// for a MachineOperand.
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MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
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const MCInstrDesc &MCID, bool IsIndirect,
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MachineOperand &MO, const MDNode *Variable,
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const MachineOperand &MO, const MDNode *Variable,
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const MDNode *Expr);
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/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
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/// for a MachineOperand.
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MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
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const MCInstrDesc &MCID, bool IsIndirect,
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ArrayRef<MachineOperand> MOs,
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const MDNode *Variable, const MDNode *Expr);
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/// This version of the builder builds a DBG_VALUE intrinsic
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/// for either a value in a register or a register-indirect
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/// address and inserts it at position I.
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@ -471,6 +478,14 @@ MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineOperand &MO, const MDNode *Variable,
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const MDNode *Expr);
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/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
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/// for a machine operand and inserts it at position I.
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MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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const MCInstrDesc &MCID, bool IsIndirect,
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ArrayRef<MachineOperand> MOs,
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const MDNode *Variable, const MDNode *Expr);
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/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
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MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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@ -2771,6 +2771,14 @@ public:
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static DIExpression *appendToStack(const DIExpression *Expr,
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ArrayRef<uint64_t> Ops);
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/// Create a copy of \p Expr by appending the given list of \p Ops to each
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/// instance of the operand `DW_OP_LLVM_arg, \p ArgNo`. This is used to
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/// modify a specific location used by \p Expr, such as when salvaging that
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/// location.
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static DIExpression *appendOpsToArg(const DIExpression *Expr,
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ArrayRef<uint64_t> Ops, unsigned ArgNo,
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bool StackValue = false);
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/// Create a DIExpression to describe one part of an aggregate variable that
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/// is fragmented across multiple Values. The DW_OP_LLVM_fragment operation
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/// will be appended to the elements of \c Expr. If \c Expr already contains
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@ -77,6 +77,10 @@ HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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HANDLE_TARGET_OPCODE(DBG_VALUE)
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic
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/// list of locations
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HANDLE_TARGET_OPCODE(DBG_VALUE_LIST)
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/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction
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/// that defines the value, rather than a virtual register.
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HANDLE_TARGET_OPCODE(DBG_INSTR_REF)
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@ -1107,6 +1107,12 @@ def DBG_VALUE : StandardPseudoInstruction {
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let AsmString = "DBG_VALUE";
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let hasSideEffects = false;
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}
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def DBG_VALUE_LIST : StandardPseudoInstruction {
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let OutOperandList = (outs);
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let InOperandList = (ins variable_ops);
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let AsmString = "DBG_VALUE_LIST";
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let hasSideEffects = 0;
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}
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def DBG_INSTR_REF : StandardPseudoInstruction {
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let OutOperandList = (outs);
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let InOperandList = (ins variable_ops);
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@ -153,6 +153,8 @@ StringRef llvm::dwarf::OperationEncodingString(unsigned Encoding) {
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return "DW_OP_LLVM_entry_value";
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case DW_OP_LLVM_implicit_pointer:
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return "DW_OP_LLVM_implicit_pointer";
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case DW_OP_LLVM_arg:
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return "DW_OP_LLVM_arg";
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}
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}
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@ -166,6 +168,7 @@ unsigned llvm::dwarf::getOperationEncoding(StringRef OperationEncodingString) {
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.Case("DW_OP_LLVM_tag_offset", DW_OP_LLVM_tag_offset)
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.Case("DW_OP_LLVM_entry_value", DW_OP_LLVM_entry_value)
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.Case("DW_OP_LLVM_implicit_pointer", DW_OP_LLVM_implicit_pointer)
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.Case("DW_OP_LLVM_arg", DW_OP_LLVM_arg)
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.Default(0);
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}
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@ -905,7 +905,7 @@ static void emitKill(const MachineInstr *MI, AsmPrinter &AP) {
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/// means the target will need to handle MI in EmitInstruction.
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static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) {
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// This code handles only the 4-operand target-independent form.
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if (MI->getNumOperands() != 4)
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if (MI->isNonListDebugValue() && MI->getNumOperands() != 4)
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return false;
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SmallString<128> Str;
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@ -1228,6 +1228,7 @@ void AsmPrinter::emitFunctionBody() {
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emitInlineAsm(&MI);
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break;
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case TargetOpcode::DBG_VALUE:
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case TargetOpcode::DBG_VALUE_LIST:
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if (isVerbose()) {
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if (!emitDebugValueComment(&MI, *this))
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emitInstruction(&MI);
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@ -235,7 +235,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
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MachineBasicBlock::iterator EndIter = std::next(MI.getIterator());
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if (MI.getOperand(0).isReg())
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for (; EndIter != MBB.end() && EndIter->isDebugValue() &&
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EndIter->getDebugOperandForReg(MI.getOperand(0).getReg());
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EndIter->hasDebugOperandForReg(MI.getOperand(0).getReg());
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++EndIter, ++Next)
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IOM[&*EndIter] = NewOrder;
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MBB.splice(I, &MBB, MI.getIterator(), EndIter);
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@ -987,7 +987,9 @@ bool MIParser::parse(MachineInstr *&MI) {
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Optional<unsigned> TiedDefIdx;
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if (parseMachineOperandAndTargetFlags(OpCode, Operands.size(), MO, TiedDefIdx))
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return true;
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if (OpCode == TargetOpcode::DBG_VALUE && MO.isReg())
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if ((OpCode == TargetOpcode::DBG_VALUE ||
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OpCode == TargetOpcode::DBG_VALUE_LIST) &&
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MO.isReg())
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MO.setIsDebug();
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Operands.push_back(
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ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
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@ -841,28 +841,35 @@ const DILabel *MachineInstr::getDebugLabel() const {
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}
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const MachineOperand &MachineInstr::getDebugVariableOp() const {
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
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return getOperand(2);
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
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unsigned VariableOp = isDebugValueList() ? 0 : 2;
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return getOperand(VariableOp);
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}
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MachineOperand &MachineInstr::getDebugVariableOp() {
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
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return getOperand(2);
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
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unsigned VariableOp = isDebugValueList() ? 0 : 2;
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return getOperand(VariableOp);
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}
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const DILocalVariable *MachineInstr::getDebugVariable() const {
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
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return cast<DILocalVariable>(getOperand(2).getMetadata());
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return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
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}
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const MachineOperand &MachineInstr::getDebugExpressionOp() const {
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
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unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
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return getOperand(ExpressionOp);
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}
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MachineOperand &MachineInstr::getDebugExpressionOp() {
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
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return getOperand(3);
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assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
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unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
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return getOperand(ExpressionOp);
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}
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const DIExpression *MachineInstr::getDebugExpression() const {
|
||||
assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
|
||||
return cast<DIExpression>(getOperand(3).getMetadata());
|
||||
return cast<DIExpression>(getDebugExpressionOp().getMetadata());
|
||||
}
|
||||
|
||||
bool MachineInstr::isDebugEntryValue() const {
|
||||
@ -1712,7 +1719,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
|
||||
OS << " ";
|
||||
|
||||
if (isDebugValue() && MO.isMetadata()) {
|
||||
// Pretty print DBG_VALUE instructions.
|
||||
// Pretty print DBG_VALUE* instructions.
|
||||
auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
|
||||
if (DIV && !DIV->getName().empty())
|
||||
OS << "!\"" << DIV->getName() << '\"';
|
||||
@ -2116,8 +2123,8 @@ MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
|
||||
|
||||
MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
|
||||
const MCInstrDesc &MCID, bool IsIndirect,
|
||||
MachineOperand &MO, const MDNode *Variable,
|
||||
const MDNode *Expr) {
|
||||
const MachineOperand &MO,
|
||||
const MDNode *Variable, const MDNode *Expr) {
|
||||
assert(isa<DILocalVariable>(Variable) && "not a variable");
|
||||
assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
|
||||
assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
|
||||
@ -2131,7 +2138,28 @@ MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
|
||||
else
|
||||
MIB.addReg(0U, RegState::Debug);
|
||||
return MIB.addMetadata(Variable).addMetadata(Expr);
|
||||
}
|
||||
}
|
||||
|
||||
MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
|
||||
const MCInstrDesc &MCID, bool IsIndirect,
|
||||
ArrayRef<MachineOperand> MOs,
|
||||
const MDNode *Variable, const MDNode *Expr) {
|
||||
assert(isa<DILocalVariable>(Variable) && "not a variable");
|
||||
assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
|
||||
assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
|
||||
"Expected inlined-at fields to agree");
|
||||
if (MCID.Opcode == TargetOpcode::DBG_VALUE)
|
||||
return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
|
||||
|
||||
auto MIB = BuildMI(MF, DL, MCID);
|
||||
MIB.addMetadata(Variable).addMetadata(Expr);
|
||||
for (const MachineOperand &MO : MOs)
|
||||
if (MO.isReg())
|
||||
MIB.addReg(MO.getReg(), RegState::Debug);
|
||||
else
|
||||
MIB.add(MO);
|
||||
return MIB;
|
||||
}
|
||||
|
||||
MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
|
||||
MachineBasicBlock::iterator I,
|
||||
@ -2155,10 +2183,22 @@ MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
|
||||
return MachineInstrBuilder(MF, *MI);
|
||||
}
|
||||
|
||||
MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
|
||||
MachineBasicBlock::iterator I,
|
||||
const DebugLoc &DL, const MCInstrDesc &MCID,
|
||||
bool IsIndirect, ArrayRef<MachineOperand> MOs,
|
||||
const MDNode *Variable, const MDNode *Expr) {
|
||||
MachineFunction &MF = *BB.getParent();
|
||||
MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
|
||||
BB.insert(I, MI);
|
||||
return MachineInstrBuilder(MF, *MI);
|
||||
}
|
||||
|
||||
/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
|
||||
/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
|
||||
static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
|
||||
assert(MI.getOperand(0).isReg() && "can't spill non-register");
|
||||
static const DIExpression *computeExprForSpill(const MachineInstr &MI,
|
||||
Register SpillReg) {
|
||||
assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
|
||||
assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
|
||||
"Expected inlined-at fields to agree");
|
||||
|
||||
@ -2167,6 +2207,14 @@ static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
|
||||
assert(MI.getDebugOffset().getImm() == 0 &&
|
||||
"DBG_VALUE with nonzero offset");
|
||||
Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
|
||||
} else if (MI.isDebugValueList()) {
|
||||
// We will replace the spilled register with a frame index, so
|
||||
// immediately deref all references to the spilled register.
|
||||
std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
|
||||
for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg)) {
|
||||
unsigned OpIdx = MI.getDebugOperandIndex(&Op);
|
||||
Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
|
||||
}
|
||||
}
|
||||
return Expr;
|
||||
}
|
||||
@ -2175,18 +2223,32 @@ MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
|
||||
MachineBasicBlock::iterator I,
|
||||
const MachineInstr &Orig,
|
||||
int FrameIndex) {
|
||||
const DIExpression *Expr = computeExprForSpill(Orig);
|
||||
return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
|
||||
.addFrameIndex(FrameIndex)
|
||||
.addImm(0U)
|
||||
.addMetadata(Orig.getDebugVariable())
|
||||
.addMetadata(Expr);
|
||||
Register SpillReg = Orig.getDebugOperand(0).getReg();
|
||||
const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
|
||||
MachineInstrBuilder NewMI =
|
||||
BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
|
||||
// Non-Variadic Operands: Location, Offset, Variable, Expression
|
||||
// Variadic Operands: Variable, Expression, Locations...
|
||||
if (Orig.isNonListDebugValue())
|
||||
NewMI.addFrameIndex(FrameIndex).addImm(0U);
|
||||
NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
|
||||
if (Orig.isDebugValueList()) {
|
||||
for (const MachineOperand &Op : Orig.debug_operands())
|
||||
if (Op.isReg() && Op.getReg() == SpillReg)
|
||||
NewMI.addFrameIndex(FrameIndex);
|
||||
else
|
||||
NewMI.add(MachineOperand(Op));
|
||||
}
|
||||
return NewMI;
|
||||
}
|
||||
|
||||
void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
|
||||
const DIExpression *Expr = computeExprForSpill(Orig);
|
||||
Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex);
|
||||
Register SpillReg = Orig.getDebugOperand(0).getReg();
|
||||
const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
|
||||
if (Orig.isNonListDebugValue())
|
||||
Orig.getDebugOffset().ChangeToImmediate(0U);
|
||||
for (MachineOperand &Op : Orig.getDebugOperandsForReg(SpillReg))
|
||||
Op.ChangeToFrameIndex(FrameIndex);
|
||||
Orig.getDebugExpressionOp().setMetadata(Expr);
|
||||
}
|
||||
|
||||
@ -2201,7 +2263,7 @@ void MachineInstr::collectDebugValues(
|
||||
DI != DE; ++DI) {
|
||||
if (!DI->isDebugValue())
|
||||
return;
|
||||
if (DI->getDebugOperandForReg(MI.getOperand(0).getReg()))
|
||||
if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
|
||||
DbgValues.push_back(&*DI);
|
||||
}
|
||||
}
|
||||
@ -2219,14 +2281,15 @@ void MachineInstr::changeDebugValuesDefReg(Register Reg) {
|
||||
auto *DI = MO.getParent();
|
||||
if (!DI->isDebugValue())
|
||||
continue;
|
||||
if (DI->getDebugOperandForReg(DefReg)) {
|
||||
if (DI->hasDebugOperandForReg(DefReg)) {
|
||||
DbgValues.push_back(DI);
|
||||
}
|
||||
}
|
||||
|
||||
// Propagate Reg to debug value instructions.
|
||||
for (auto *DBI : DbgValues)
|
||||
DBI->getDebugOperandForReg(DefReg)->setReg(Reg);
|
||||
for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
|
||||
Op.setReg(Reg);
|
||||
}
|
||||
|
||||
using MMOList = SmallVector<const MachineMemOperand *, 2>;
|
||||
|
||||
@ -530,11 +530,11 @@ bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
|
||||
/// specified register as undefined which causes the DBG_VALUE to be
|
||||
/// deleted during LiveDebugVariables analysis.
|
||||
void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
|
||||
// Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
|
||||
// Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
|
||||
// We use make_early_inc_range because setReg invalidates the iterator.
|
||||
for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) {
|
||||
if (UseMI.isDebugValue())
|
||||
UseMI.getDebugOperandForReg(Reg)->setReg(0U);
|
||||
if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
|
||||
UseMI.setDebugValueUndef();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1233,6 +1233,8 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
|
||||
// complex location that is interpreted as being a memory address.
|
||||
// This changes a pointer-valued variable to dereference that pointer,
|
||||
// which is incorrect. Fix by adding DW_OP_stack_value.
|
||||
|
||||
if (MI.isNonListDebugValue()) {
|
||||
unsigned PrependFlags = DIExpression::ApplyOffset;
|
||||
if (!MI.isIndirectDebugValue() && !DIExpr->isComplex())
|
||||
PrependFlags |= DIExpression::StackValue;
|
||||
@ -1248,8 +1250,16 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
|
||||
// Make the DBG_VALUE direct.
|
||||
MI.getDebugOffset().ChangeToRegister(0, false);
|
||||
}
|
||||
|
||||
DIExpr = TRI.prependOffsetExpression(DIExpr, PrependFlags, Offset);
|
||||
} else {
|
||||
// The debug operand at DebugOpIndex was a frame index at offset
|
||||
// `Offset`; now the operand has been replaced with the frame
|
||||
// register, we must add Offset with `register x, plus Offset`.
|
||||
unsigned DebugOpIndex = MI.getDebugOperandIndex(&MI.getOperand(i));
|
||||
SmallVector<uint64_t, 3> Ops;
|
||||
TRI.getOffsetOpcodes(Offset, Ops);
|
||||
DIExpr = DIExpression::appendOpsToArg(DIExpr, Ops, DebugOpIndex);
|
||||
}
|
||||
MI.getDebugExpressionOp().setMetadata(DIExpr);
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -424,10 +424,15 @@ void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg,
|
||||
}
|
||||
|
||||
// Rewrite unassigned dbg_values to use the stack slot.
|
||||
MachineOperand &MO = DBG->getOperand(0);
|
||||
if (MO.isReg() && MO.getReg() == 0)
|
||||
// TODO We can potentially do this for list debug values as well if we know
|
||||
// how the dbg_values are getting unassigned.
|
||||
if (DBG->isNonListDebugValue()) {
|
||||
MachineOperand &MO = DBG->getDebugOperand(0);
|
||||
if (MO.isReg() && MO.getReg() == 0) {
|
||||
updateDbgValueForSpill(*DBG, FI);
|
||||
}
|
||||
}
|
||||
}
|
||||
// Now this register is spilled there is should not be any DBG_VALUE
|
||||
// pointing to this register because they are all pointing to spilled value
|
||||
// now.
|
||||
@ -623,8 +628,7 @@ void RegAllocFast::assignDanglingDebugValues(MachineInstr &Definition,
|
||||
SmallVectorImpl<MachineInstr*> &Dangling = UDBGValIter->second;
|
||||
for (MachineInstr *DbgValue : Dangling) {
|
||||
assert(DbgValue->isDebugValue());
|
||||
MachineOperand &MO = DbgValue->getOperand(0);
|
||||
if (!MO.isReg())
|
||||
if (!DbgValue->hasDebugOperandForReg(VirtReg))
|
||||
continue;
|
||||
|
||||
// Test whether the physreg survives from the definition to the DBG_VALUE.
|
||||
@ -639,10 +643,12 @@ void RegAllocFast::assignDanglingDebugValues(MachineInstr &Definition,
|
||||
break;
|
||||
}
|
||||
}
|
||||
for (MachineOperand &MO : DbgValue->getDebugOperandsForReg(VirtReg)) {
|
||||
MO.setReg(SetToReg);
|
||||
if (SetToReg != 0)
|
||||
MO.setIsRenamable();
|
||||
}
|
||||
}
|
||||
Dangling.clear();
|
||||
}
|
||||
|
||||
@ -1360,15 +1366,19 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
|
||||
}
|
||||
|
||||
void RegAllocFast::handleDebugValue(MachineInstr &MI) {
|
||||
MachineOperand &MO = MI.getDebugOperand(0);
|
||||
|
||||
SmallSet<Register, 4> SeenRegisters;
|
||||
for (MachineOperand &MO : MI.debug_operands()) {
|
||||
// Ignore DBG_VALUEs that aren't based on virtual registers. These are
|
||||
// mostly constants and frame indices.
|
||||
if (!MO.isReg())
|
||||
return;
|
||||
continue;
|
||||
Register Reg = MO.getReg();
|
||||
if (!Register::isVirtualRegister(Reg))
|
||||
return;
|
||||
continue;
|
||||
// Only process each register once per MI, each use of that register will
|
||||
// be updated if necessary.
|
||||
if (!SeenRegisters.insert(Reg).second)
|
||||
continue;
|
||||
|
||||
// Already spilled to a stackslot?
|
||||
int SS = StackSlotForVirtReg[Reg];
|
||||
@ -1376,14 +1386,16 @@ void RegAllocFast::handleDebugValue(MachineInstr &MI) {
|
||||
// Modify DBG_VALUE now that the value is in a spill slot.
|
||||
updateDbgValueForSpill(MI, SS);
|
||||
LLVM_DEBUG(dbgs() << "Rewrite DBG_VALUE for spilled memory: " << MI);
|
||||
return;
|
||||
continue;
|
||||
}
|
||||
|
||||
// See if this virtual register has already been allocated to a physical
|
||||
// register or spilled to a stack slot.
|
||||
LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
|
||||
if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
|
||||
setPhysReg(MI, MO, LRI->PhysReg);
|
||||
// Update every use of Reg within MI.
|
||||
for (auto &RegMO : MI.getDebugOperandsForReg(Reg))
|
||||
setPhysReg(MI, RegMO, LRI->PhysReg);
|
||||
} else {
|
||||
DanglingDbgValues[Reg].push_back(&MI);
|
||||
}
|
||||
@ -1391,6 +1403,7 @@ void RegAllocFast::handleDebugValue(MachineInstr &MI) {
|
||||
// If Reg hasn't been spilled, put this DBG_VALUE in LiveDbgValueMap so
|
||||
// that future spills of Reg will have DBG_VALUEs.
|
||||
LiveDbgValueMap[Reg].push_back(&MI);
|
||||
}
|
||||
}
|
||||
|
||||
void RegAllocFast::handleBundle(MachineInstr &MI) {
|
||||
@ -1472,13 +1485,12 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
for (auto &UDBGPair : DanglingDbgValues) {
|
||||
for (MachineInstr *DbgValue : UDBGPair.second) {
|
||||
assert(DbgValue->isDebugValue() && "expected DBG_VALUE");
|
||||
MachineOperand &MO = DbgValue->getOperand(0);
|
||||
// Nothing to do if the vreg was spilled in the meantime.
|
||||
if (!MO.isReg())
|
||||
if (!DbgValue->hasDebugOperandForReg(UDBGPair.first))
|
||||
continue;
|
||||
LLVM_DEBUG(dbgs() << "Register did not survive for " << *DbgValue
|
||||
<< '\n');
|
||||
MO.setReg(0);
|
||||
DbgValue->setDebugValueUndef();
|
||||
}
|
||||
}
|
||||
DanglingDbgValues.clear();
|
||||
|
||||
@ -1059,6 +1059,7 @@ unsigned DIExpression::ExprOperand::getSize() const {
|
||||
case dwarf::DW_OP_plus_uconst:
|
||||
case dwarf::DW_OP_LLVM_tag_offset:
|
||||
case dwarf::DW_OP_LLVM_entry_value:
|
||||
case dwarf::DW_OP_LLVM_arg:
|
||||
case dwarf::DW_OP_regx:
|
||||
return 2;
|
||||
default:
|
||||
@ -1115,6 +1116,7 @@ bool DIExpression::isValid() const {
|
||||
}
|
||||
case dwarf::DW_OP_LLVM_implicit_pointer:
|
||||
case dwarf::DW_OP_LLVM_convert:
|
||||
case dwarf::DW_OP_LLVM_arg:
|
||||
case dwarf::DW_OP_LLVM_tag_offset:
|
||||
case dwarf::DW_OP_constu:
|
||||
case dwarf::DW_OP_plus_uconst:
|
||||
@ -1270,6 +1272,30 @@ DIExpression *DIExpression::prepend(const DIExpression *Expr, uint8_t Flags,
|
||||
return prependOpcodes(Expr, Ops, StackValue, EntryValue);
|
||||
}
|
||||
|
||||
DIExpression *DIExpression::appendOpsToArg(const DIExpression *Expr,
|
||||
ArrayRef<uint64_t> Ops,
|
||||
unsigned ArgNo, bool StackValue) {
|
||||
assert(Expr && "Can't add ops to this expression");
|
||||
|
||||
// Handle non-variadic intrinsics by prepending the opcodes.
|
||||
if (!any_of(Expr->expr_ops(),
|
||||
[](auto Op) { return Op.getOp() == dwarf::DW_OP_LLVM_arg; })) {
|
||||
assert(ArgNo == 0 &&
|
||||
"Location Index must be 0 for a non-variadic expression.");
|
||||
SmallVector<uint64_t, 8> NewOps(Ops.begin(), Ops.end());
|
||||
return DIExpression::prependOpcodes(Expr, NewOps, StackValue);
|
||||
}
|
||||
|
||||
SmallVector<uint64_t, 8> NewOps;
|
||||
for (auto Op : Expr->expr_ops()) {
|
||||
Op.appendToVector(NewOps);
|
||||
if (Op.getOp() == dwarf::DW_OP_LLVM_arg && Op.getArg(0) == ArgNo)
|
||||
NewOps.insert(NewOps.end(), Ops.begin(), Ops.end());
|
||||
}
|
||||
|
||||
return DIExpression::get(Expr->getContext(), NewOps);
|
||||
}
|
||||
|
||||
DIExpression *DIExpression::prependOpcodes(const DIExpression *Expr,
|
||||
SmallVectorImpl<uint64_t> &Ops,
|
||||
bool StackValue,
|
||||
|
||||
@ -1210,7 +1210,8 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
|
||||
}
|
||||
break;
|
||||
|
||||
case AArch64::DBG_VALUE: {
|
||||
case AArch64::DBG_VALUE:
|
||||
case AArch64::DBG_VALUE_LIST: {
|
||||
if (isVerbose() && OutStreamer->hasRawTextSupport()) {
|
||||
SmallString<128> TmpStr;
|
||||
raw_svector_ostream OS(TmpStr);
|
||||
|
||||
@ -65,16 +65,25 @@ bool NVPTXPrologEpilogPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
// way with simply the frame index and offset rather than any
|
||||
// target-specific addressing mode.
|
||||
if (MI.isDebugValue()) {
|
||||
assert(i == 0 && "Frame indices can only appear as the first "
|
||||
"operand of a DBG_VALUE machine instruction");
|
||||
MachineOperand &Op = MI.getOperand(i);
|
||||
assert(
|
||||
MI.isDebugOperand(&Op) &&
|
||||
"Frame indices can only appear as a debug operand in a DBG_VALUE*"
|
||||
" machine instruction");
|
||||
Register Reg;
|
||||
int64_t Offset =
|
||||
TFI.getFrameIndexReference(MF, MI.getOperand(0).getIndex(), Reg)
|
||||
.getFixed();
|
||||
MI.getOperand(0).ChangeToRegister(Reg, /*isDef=*/false);
|
||||
MI.getOperand(0).setIsDebug();
|
||||
auto *DIExpr = DIExpression::prepend(
|
||||
MI.getDebugExpression(), DIExpression::ApplyOffset, Offset);
|
||||
auto Offset =
|
||||
TFI.getFrameIndexReference(MF, Op.getIndex(), Reg);
|
||||
Op.ChangeToRegister(Reg, /*isDef=*/false);
|
||||
Op.setIsDebug();
|
||||
const DIExpression *DIExpr = MI.getDebugExpression();
|
||||
if (MI.isNonListDebugValue()) {
|
||||
DIExpr = TRI.prependOffsetExpression(MI.getDebugExpression(), DIExpression::ApplyOffset, Offset);
|
||||
} else {
|
||||
SmallVector<uint64_t, 3> Ops;
|
||||
TRI.getOffsetOpcodes(Offset, Ops);
|
||||
unsigned OpIdx = MI.getDebugOperandIndex(&Op);
|
||||
DIExpr = DIExpression::appendOpsToArg(DIExpr, Ops, OpIdx);
|
||||
}
|
||||
MI.getDebugExpressionOp().setMetadata(DIExpr);
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -9,12 +9,13 @@
|
||||
#include "SystemZRegisterInfo.h"
|
||||
#include "SystemZInstrInfo.h"
|
||||
#include "SystemZSubtarget.h"
|
||||
#include "llvm/CodeGen/LiveIntervals.h"
|
||||
#include "llvm/ADT/SmallSet.h"
|
||||
#include "llvm/CodeGen/LiveIntervals.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/TargetFrameLowering.h"
|
||||
#include "llvm/CodeGen/VirtRegMap.h"
|
||||
#include "llvm/IR/DebugInfoMetadata.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -273,7 +274,16 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
// Special handling of dbg_value instructions.
|
||||
if (MI->isDebugValue()) {
|
||||
MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
|
||||
if (MI->isNonListDebugValue()) {
|
||||
MI->getDebugOffset().ChangeToImmediate(Offset);
|
||||
} else {
|
||||
unsigned OpIdx = MI->getDebugOperandIndex(&MI->getOperand(FIOperandNum));
|
||||
SmallVector<uint64_t, 3> Ops;
|
||||
DIExpression::appendOffset(
|
||||
Ops, TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed());
|
||||
MI->getDebugExpressionOp().setMetadata(
|
||||
DIExpression::appendOpsToArg(MI->getDebugExpression(), Ops, OpIdx));
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -30,7 +30,7 @@ WebAssemblyDebugValueManager::WebAssemblyDebugValueManager(
|
||||
for (MachineBasicBlock::iterator DE = Instr->getParent()->end(); DI != DE;
|
||||
++DI) {
|
||||
if (DI->isDebugValue() &&
|
||||
DI->getDebugOperandForReg(Instr->getOperand(0).getReg()))
|
||||
DI->hasDebugOperandForReg(Instr->getOperand(0).getReg()))
|
||||
DbgValues.push_back(&*DI);
|
||||
}
|
||||
}
|
||||
|
||||
@ -295,8 +295,8 @@ private:
|
||||
/// Replace debug value MI with a new debug value instruction using register
|
||||
/// VReg with an appropriate offset and DIExpression to incorporate the
|
||||
/// address displacement AddrDispShift. Return new debug value instruction.
|
||||
MachineInstr *replaceDebugValue(MachineInstr &MI, unsigned VReg,
|
||||
int64_t AddrDispShift);
|
||||
MachineInstr *replaceDebugValue(MachineInstr &MI, unsigned OldReg,
|
||||
unsigned NewReg, int64_t AddrDispShift);
|
||||
|
||||
/// Removes LEAs which calculate similar addresses.
|
||||
bool removeRedundantLEAs(MemOpMap &LEAs);
|
||||
@ -576,21 +576,50 @@ bool X86OptimizeLEAPass::removeRedundantAddrCalc(MemOpMap &LEAs) {
|
||||
}
|
||||
|
||||
MachineInstr *X86OptimizeLEAPass::replaceDebugValue(MachineInstr &MI,
|
||||
unsigned VReg,
|
||||
unsigned OldReg,
|
||||
unsigned NewReg,
|
||||
int64_t AddrDispShift) {
|
||||
const DIExpression *Expr = MI.getDebugExpression();
|
||||
if (AddrDispShift != 0)
|
||||
Expr = DIExpression::prepend(Expr, DIExpression::StackValue, AddrDispShift);
|
||||
if (AddrDispShift != 0) {
|
||||
if (MI.isNonListDebugValue()) {
|
||||
Expr =
|
||||
DIExpression::prepend(Expr, DIExpression::StackValue, AddrDispShift);
|
||||
} else {
|
||||
// Update the Expression, appending an offset of `AddrDispShift` to the
|
||||
// Op corresponding to `OldReg`.
|
||||
SmallVector<uint64_t, 3> Ops;
|
||||
DIExpression::appendOffset(Ops, AddrDispShift);
|
||||
for (MachineOperand &Op : MI.getDebugOperandsForReg(OldReg)) {
|
||||
unsigned OpIdx = MI.getDebugOperandIndex(&Op);
|
||||
Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Replace DBG_VALUE instruction with modified version.
|
||||
MachineBasicBlock *MBB = MI.getParent();
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
bool IsIndirect = MI.isIndirectDebugValue();
|
||||
const MDNode *Var = MI.getDebugVariable();
|
||||
unsigned Opcode = MI.isNonListDebugValue() ? TargetOpcode::DBG_VALUE
|
||||
: TargetOpcode::DBG_VALUE_LIST;
|
||||
if (IsIndirect)
|
||||
assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
|
||||
return BuildMI(*MBB, MBB->erase(&MI), DL, TII->get(TargetOpcode::DBG_VALUE),
|
||||
IsIndirect, VReg, Var, Expr);
|
||||
assert(MI.getDebugOffset().getImm() == 0 &&
|
||||
"DBG_VALUE with nonzero offset");
|
||||
SmallVector<MachineOperand, 4> NewOps;
|
||||
// If we encounter an operand using the old register, replace it with an
|
||||
// operand that uses the new register; otherwise keep the old operand.
|
||||
auto replaceOldReg = [OldReg, NewReg](const MachineOperand &Op) {
|
||||
if (Op.isReg() && Op.getReg() == OldReg)
|
||||
return MachineOperand::CreateReg(NewReg, false, false, false, false,
|
||||
false, false, false, false, 0,
|
||||
/*IsRenamable*/ true);
|
||||
return Op;
|
||||
};
|
||||
for (const MachineOperand &Op : MI.debug_operands())
|
||||
NewOps.push_back(replaceOldReg(Op));
|
||||
return BuildMI(*MBB, MBB->erase(&MI), DL, TII->get(Opcode), IsIndirect,
|
||||
NewOps, Var, Expr);
|
||||
}
|
||||
|
||||
// Try to find similar LEAs in the list and replace one with another.
|
||||
@ -635,7 +664,7 @@ bool X86OptimizeLEAPass::removeRedundantLEAs(MemOpMap &LEAs) {
|
||||
// Replace DBG_VALUE instruction with modified version using the
|
||||
// register from the replacing LEA and the address displacement
|
||||
// between the LEA instructions.
|
||||
replaceDebugValue(MI, FirstVReg, AddrDispShift);
|
||||
replaceDebugValue(MI, LastVReg, FirstVReg, AddrDispShift);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
64
test/CodeGen/MIR/X86/dbg-value-list.mir
Normal file
64
test/CodeGen/MIR/X86/dbg-value-list.mir
Normal file
@ -0,0 +1,64 @@
|
||||
# RUN: llc -march=x86-64 -run-pass machineverifier -o - %s | FileCheck %s
|
||||
# Simple round-trip test for DBG_VALUE_LIST.
|
||||
# CHECK: [[VAR_C:![0-9]+]] = !DILocalVariable(name: "c"
|
||||
# CHECK: DBG_VALUE_LIST [[VAR_C]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $edi, $esi, debug-location
|
||||
--- |
|
||||
; ModuleID = 'test.cpp'
|
||||
source_filename = "test.cpp"
|
||||
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone uwtable
|
||||
define dso_local i32 @_Z3fooii(i32 %a, i32 %b) local_unnamed_addr !dbg !7 {
|
||||
entry:
|
||||
call void @llvm.dbg.value(metadata i32 %a, metadata !12, metadata !DIExpression()), !dbg !15
|
||||
call void @llvm.dbg.value(metadata i32 %b, metadata !13, metadata !DIExpression()), !dbg !15
|
||||
call void @llvm.dbg.value(metadata i32 undef, metadata !14, metadata !DIExpression()), !dbg !15
|
||||
%mul = mul nsw i32 %b, %a, !dbg !16
|
||||
ret i32 %mul, !dbg !17
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone speculatable willreturn
|
||||
declare void @llvm.dbg.value(metadata, metadata, metadata)
|
||||
|
||||
!llvm.dbg.cu = !{!0}
|
||||
!llvm.module.flags = !{!3, !4, !5}
|
||||
!llvm.ident = !{!6}
|
||||
|
||||
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 11.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
|
||||
!1 = !DIFile(filename: "test.cpp", directory: "/")
|
||||
!2 = !{}
|
||||
!3 = !{i32 7, !"Dwarf Version", i32 4}
|
||||
!4 = !{i32 2, !"Debug Info Version", i32 3}
|
||||
!5 = !{i32 1, !"wchar_size", i32 4}
|
||||
!6 = !{!"clang version 11.0.0"}
|
||||
!7 = distinct !DISubprogram(name: "foo", linkageName: "_Z3fooii", scope: !1, file: !1, line: 2, type: !8, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !11)
|
||||
!8 = !DISubroutineType(types: !9)
|
||||
!9 = !{!10, !10, !10}
|
||||
!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
|
||||
!11 = !{!12, !13, !14}
|
||||
!12 = !DILocalVariable(name: "a", arg: 1, scope: !7, file: !1, line: 2, type: !10)
|
||||
!13 = !DILocalVariable(name: "b", arg: 2, scope: !7, file: !1, line: 2, type: !10)
|
||||
!14 = !DILocalVariable(name: "c", scope: !7, file: !1, line: 3, type: !10)
|
||||
!15 = !DILocation(line: 0, scope: !7)
|
||||
!16 = !DILocation(line: 4, column: 12, scope: !7)
|
||||
!17 = !DILocation(line: 4, column: 3, scope: !7)
|
||||
|
||||
...
|
||||
---
|
||||
name: _Z3fooii
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $edi, $esi
|
||||
|
||||
DBG_VALUE $edi, $noreg, !12, !DIExpression(), debug-location !15
|
||||
DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !15
|
||||
$eax = MOV32rr $edi
|
||||
DBG_VALUE_LIST !14, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $edi, $esi, debug-location !15
|
||||
DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !15
|
||||
DBG_VALUE $eax, $noreg, !12, !DIExpression(), debug-location !15
|
||||
renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $esi, implicit-def dead $eflags, debug-location !16
|
||||
RETQ $eax, debug-location !17
|
||||
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user