diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index b27a02b8c18..60c00f47859 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -13680,6 +13680,8 @@ static bool isEssentiallyExtractHighSubvector(SDValue N) {
     N = N.getOperand(0);
   if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR)
     return false;
+  if (N.getOperand(0).getValueType().isScalableVector())
+    return false;
   return cast<ConstantSDNode>(N.getOperand(1))->getAPIntValue() ==
          N.getOperand(0).getValueType().getVectorNumElements() / 2;
 }
diff --git a/test/CodeGen/AArch64/sve-no-typesize-warnings.ll b/test/CodeGen/AArch64/sve-no-typesize-warnings.ll
new file mode 100644
index 00000000000..3492d9a1636
--- /dev/null
+++ b/test/CodeGen/AArch64/sve-no-typesize-warnings.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define <4 x i32> @sve_no_typesize_warning(<vscale x 8 x i16> %a, <4 x i16> %b) #0 {
+; CHECK-LABEL: sve_no_typesize_warning:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uaddl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
+%a.lo = call <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16> %a, i64 0)
+%a.lo.zext = zext <4 x i16> %a.lo to <4 x i32>
+%b.zext = zext <4 x i16> %b to <4 x i32>
+%add = add <4 x i32> %a.lo.zext, %b.zext
+ret <4 x i32> %add
+}
+
+declare <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16>, i64)
+
+attributes #0 = { "target-features"="+sve" }