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AMDGPU/GlobalISel: Refactor special argument management
This commit is contained in:
Matt Arsenault
parent
72b7484d1d
commit
e11e91bb11
@ -993,7 +993,7 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
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Register InputReg = MRI.createGenericVirtualRegister(ArgTy);
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if (IncomingArg) {
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LI->loadInputValue(InputReg, MIRBuilder, IncomingArg);
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LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
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} else {
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assert(InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
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LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder);
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@ -1026,13 +1026,16 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
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if (!OutgoingArg)
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return false;
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const ArgDescriptor *IncomingArgX = std::get<0>(
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CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X));
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const ArgDescriptor *IncomingArgY = std::get<0>(
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CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y));
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const ArgDescriptor *IncomingArgZ = std::get<0>(
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CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z));
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auto WorkitemIDX =
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CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
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auto WorkitemIDY =
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CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
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auto WorkitemIDZ =
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CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
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const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX);
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const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY);
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const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ);
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const LLT S32 = LLT::scalar(32);
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// If incoming ids are not packed we need to pack them.
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@ -1040,12 +1043,14 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
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Register InputReg;
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if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX) {
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InputReg = MRI.createGenericVirtualRegister(S32);
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LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX);
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LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,
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std::get<1>(WorkitemIDX), std::get<2>(WorkitemIDX));
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}
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if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY) {
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Register Y = MRI.createGenericVirtualRegister(S32);
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LI->loadInputValue(Y, MIRBuilder, IncomingArgY);
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LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),
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std::get<2>(WorkitemIDY));
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Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);
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InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
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@ -1053,7 +1058,8 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
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if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ) {
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Register Z = MRI.createGenericVirtualRegister(S32);
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LI->loadInputValue(Z, MIRBuilder, IncomingArgZ);
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LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),
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std::get<2>(WorkitemIDZ));
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Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);
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InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
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@ -1067,7 +1073,8 @@ bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
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ArgDescriptor IncomingArg = ArgDescriptor::createArg(
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IncomingArgX ? *IncomingArgX :
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IncomingArgY ? *IncomingArgY : *IncomingArgZ, ~0u);
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LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg);
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LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,
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&AMDGPU::VGPR_32RegClass, S32);
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}
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if (OutgoingArg->isRegister()) {
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@ -1630,8 +1630,7 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
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Register QueuePtr = MRI.createGenericVirtualRegister(
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LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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if (!loadInputValue(QueuePtr, B, &MFI->getArgInfo().QueuePtr))
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if (!loadInputValue(QueuePtr, B, AMDGPUFunctionArgInfo::QUEUE_PTR))
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return Register();
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// Offset into amd_queue_t for group_segment_aperture_base_hi /
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@ -2496,33 +2495,16 @@ Register AMDGPULegalizerInfo::getLiveInRegister(MachineIRBuilder &B,
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return insertLiveInCopy(B, MRI, LiveIn, PhyReg);
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}
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const ArgDescriptor *AMDGPULegalizerInfo::getArgDescriptor(
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MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const {
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const SIMachineFunctionInfo *MFI = B.getMF().getInfo<SIMachineFunctionInfo>();
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const ArgDescriptor *Arg;
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const TargetRegisterClass *RC;
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LLT ArgTy;
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std::tie(Arg, RC, ArgTy) = MFI->getPreloadedValue(ArgType);
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if (!Arg) {
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LLVM_DEBUG(dbgs() << "Required arg register missing\n");
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return nullptr;
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}
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return Arg;
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}
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bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
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const ArgDescriptor *Arg) const {
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if (!Arg->isRegister() || !Arg->getRegister().isValid())
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return false; // TODO: Handle these
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Register SrcReg = Arg->getRegister();
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const ArgDescriptor *Arg,
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const TargetRegisterClass *ArgRC,
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LLT ArgTy) const {
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MCRegister SrcReg = Arg->getRegister();
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assert(SrcReg.isPhysical() && "Physical register expected");
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assert(DstReg.isVirtual() && "Virtual register expected");
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MachineRegisterInfo &MRI = *B.getMRI();
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LLT Ty = MRI.getType(DstReg);
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Register LiveIn = getLiveInRegister(B, MRI, SrcReg, Ty);
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Register LiveIn = getLiveInRegister(B, MRI, SrcReg, ArgTy);
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if (Arg->isMasked()) {
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// TODO: Should we try to emit this once in the entry block?
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@ -2545,15 +2527,24 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
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return true;
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}
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bool AMDGPULegalizerInfo::loadInputValue(
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Register DstReg, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const {
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const SIMachineFunctionInfo *MFI = B.getMF().getInfo<SIMachineFunctionInfo>();
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const ArgDescriptor *Arg;
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const TargetRegisterClass *ArgRC;
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LLT ArgTy;
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std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType);
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if (!Arg->isRegister() || !Arg->getRegister().isValid())
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return false; // TODO: Handle these
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return loadInputValue(DstReg, B, Arg, ArgRC, ArgTy);
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}
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bool AMDGPULegalizerInfo::legalizePreloadedArgIntrin(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const {
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const ArgDescriptor *Arg = getArgDescriptor(B, ArgType);
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if (!Arg)
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return false;
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if (!loadInputValue(MI.getOperand(0).getReg(), B, Arg))
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if (!loadInputValue(MI.getOperand(0).getReg(), B, ArgType))
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return false;
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MI.eraseFromParent();
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@ -3165,23 +3156,15 @@ bool AMDGPULegalizerInfo::legalizeFDIVFastIntrin(MachineInstr &MI,
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bool AMDGPULegalizerInfo::getImplicitArgPtr(Register DstReg,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const {
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const SIMachineFunctionInfo *MFI = B.getMF().getInfo<SIMachineFunctionInfo>();
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uint64_t Offset =
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ST.getTargetLowering()->getImplicitParameterOffset(
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B.getMF(), AMDGPUTargetLowering::FIRST_IMPLICIT);
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LLT DstTy = MRI.getType(DstReg);
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LLT IdxTy = LLT::scalar(DstTy.getSizeInBits());
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const ArgDescriptor *Arg;
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const TargetRegisterClass *RC;
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LLT ArgTy;
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std::tie(Arg, RC, ArgTy) =
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MFI->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
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if (!Arg)
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return false;
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Register KernargPtrReg = MRI.createGenericVirtualRegister(DstTy);
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if (!loadInputValue(KernargPtrReg, B, Arg))
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if (!loadInputValue(KernargPtrReg, B,
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AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR))
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return false;
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// FIXME: This should be nuw
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@ -4169,16 +4152,12 @@ bool AMDGPULegalizerInfo::legalizeTrapIntrinsic(MachineInstr &MI,
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} else {
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// Pass queue pointer to trap handler as input, and insert trap instruction
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// Reference: https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi
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const ArgDescriptor *Arg =
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getArgDescriptor(B, AMDGPUFunctionArgInfo::QUEUE_PTR);
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if (!Arg)
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return false;
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MachineRegisterInfo &MRI = *B.getMRI();
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Register SGPR01(AMDGPU::SGPR0_SGPR1);
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Register LiveIn = getLiveInRegister(
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B, MRI, SGPR01, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64),
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/*InsertLiveInCopy=*/false);
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if (!loadInputValue(LiveIn, B, Arg))
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if (!loadInputValue(LiveIn, B, AMDGPUFunctionArgInfo::QUEUE_PTR))
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return false;
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B.buildCopy(SGPR01, LiveIn);
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B.buildInstr(AMDGPU::S_TRAP)
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@ -91,11 +91,11 @@ public:
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bool InsertLiveInCopy = true) const;
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Register insertLiveInCopy(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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Register LiveIn, Register PhyReg) const;
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const ArgDescriptor *
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getArgDescriptor(MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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bool loadInputValue(Register DstReg, MachineIRBuilder &B,
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const ArgDescriptor *Arg) const;
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const ArgDescriptor *Arg,
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const TargetRegisterClass *ArgRC, LLT ArgTy) const;
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bool loadInputValue(Register DstReg, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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bool legalizePreloadedArgIntrin(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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