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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 10:42:39 +01:00
[Hexagon] Lower bitcast of a vector predicate
This patch lowers bitcast of vector predicate of type v32i1/v64i1 to i32/i64 type.
This commit is contained in:
Ikhlas Ajbar
Krzysztof Parzyszek
parent
97dadf463b
commit
e16adb830a
@ -1694,6 +1694,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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// Custom-lower bitcasts from i8 to v8i1.
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setOperationAction(ISD::BITCAST, MVT::i8, Custom);
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setOperationAction(ISD::BITCAST, MVT::i32, Custom);
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setOperationAction(ISD::BITCAST, MVT::i64, Custom);
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setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
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@ -2266,13 +2268,16 @@ HexagonTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
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const SDLoc &dl(Op);
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// Handle conversion from i8 to v8i1.
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if (ResTy == MVT::v8i1) {
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SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
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SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
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return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
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if (InpTy == MVT::i8) {
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if (ResTy == MVT::v8i1) {
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SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
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SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
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return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
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}
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return SDValue();
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}
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return SDValue();
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return Op;
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}
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bool
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@ -445,7 +445,7 @@ namespace HexagonISD {
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SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
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@ -1437,6 +1437,136 @@ HexagonTargetLowering::LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const {
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return T7;
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}
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SDValue HexagonTargetLowering::LowerHvxBitcast(SDValue Op,
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SelectionDAG &DAG) const {
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auto *N = Op.getNode();
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EVT VT = N->getValueType(0);
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const SDLoc &dl(Op);
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SDValue Q0 = N->getOperand(0);
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EVT VTOp = Q0.getNode()->getValueType(0);
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if (!(VT == MVT::i64 || VT == MVT::i32) ||
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!(VTOp == MVT::v64i1 || VTOp == MVT::v32i1)) {
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return Op;
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}
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MVT VecTy;
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int Length;
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if (Subtarget.useHVX64BOps()) {
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VecTy = MVT::getVectorVT(MVT::i32, 16);
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Length = 2;
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}
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if (Subtarget.useHVX128BOps()) {
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VecTy = MVT::getVectorVT(MVT::i32, 32);
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Length = 4;
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}
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// r0 = ##0x08040201 // Pre-rotated bits per 4 consecutive bytes.
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SDValue C8421 = DAG.getTargetConstant(0x08040201, dl, MVT::i32);
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SDValue InstrC8421 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C8421, DAG);
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// v0 = vand(q0,r0)
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SDValue Vand =
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getInstr(Hexagon::V6_vandqrt, dl, VecTy, {Q0, InstrC8421}, DAG);
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// Or the bytes in each word into a single byte: that will form packs
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// of 4 bits of the output.
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// v1 = valign(v0,v0,#2)
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SDValue C2 = DAG.getTargetConstant(2, dl, MVT::i32);
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SDValue Valign =
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getInstr(Hexagon::V6_valignbi, dl, VecTy, {Vand, Vand, C2}, DAG);
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// v0 = vor(v0,v1)
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SDValue Vor = getInstr(Hexagon::V6_vor, dl, VecTy, {Vand, Valign}, DAG);
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// v1 = valign(v0,v0,#1)
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SDValue C1 = DAG.getTargetConstant(1, dl, MVT::i32);
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SDValue Valign1 =
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getInstr(Hexagon::V6_valignbi, dl, VecTy, {Vor, Vor, C1}, DAG);
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// v0 = vor(v0,v1)
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SDValue Vor1 = getInstr(Hexagon::V6_vor, dl, VecTy, {Vor, Valign1}, DAG);
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// Clear all the bytes per word except the lowest one.
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// r0 = #0xff
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SDValue Cff = DAG.getTargetConstant(0xff, dl, MVT::i32);
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SDValue InstrCff = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, Cff, DAG);
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// v1 = vsplat(r0)
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SDValue Vsplat = getInstr(Hexagon::V6_lvsplatw, dl, VecTy, InstrCff, DAG);
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// v0 = vand(v0,v1)
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SDValue Vand1 = getInstr(Hexagon::V6_vand, dl, VecTy, {Vor1, Vsplat}, DAG);
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// Shift each word left by its index to position the 4-bit packs for oring.
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// The words 0..8 and 16..31 need to be ored to form the 64-bit output.
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// r0 = ##.Lshifts
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// .Lshifts:
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// .word 0
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// .word 4
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// .word 8
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// .word 12
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// .word 16
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// .word 20
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// .word 24
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// .word 28
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// .word 0
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// .word 4
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// .word 8
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// .word 12
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// .word 16
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// .word 20
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// .word 24
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// .word 28
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// v1 = vmem(r0+#0)
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SmallVector<SDValue, 32> Elems;
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for (int i = 0; i < Length; ++i) {
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Elems.push_back(DAG.getConstant(0, dl, MVT::i32));
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Elems.push_back(DAG.getConstant(4, dl, MVT::i32));
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Elems.push_back(DAG.getConstant(8, dl, MVT::i32));
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Elems.push_back(DAG.getConstant(12, dl, MVT::i32));
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Elems.push_back(DAG.getConstant(16, dl, MVT::i32));
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Elems.push_back(DAG.getConstant(20, dl, MVT::i32));
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Elems.push_back(DAG.getConstant(24, dl, MVT::i32));
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Elems.push_back(DAG.getConstant(28, dl, MVT::i32));
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}
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SDValue BV = DAG.getBuildVector(VecTy, dl, Elems);
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// v0.w = vasl(v0.w,v1.w)
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SDValue Vasl = getInstr(Hexagon::V6_vaslwv, dl, VecTy, {Vand1, BV}, DAG);
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// 3 rounds of oring.
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// r0 = #16 // HwLen/4
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SDValue C16 = DAG.getTargetConstant(16, dl, MVT::i32);
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SDValue InstrC16 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C16, DAG);
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// v1 = vror(v0,r0)
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SDValue Vror = getInstr(Hexagon::V6_vror, dl, VecTy, {Vasl, InstrC16}, DAG);
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// v0 = vor(v0,v1)
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SDValue Vor2 = getInstr(Hexagon::V6_vor, dl, VecTy, {Vasl, Vror}, DAG);
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// r0 = #8 // HwLen/8
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SDValue C8 = DAG.getTargetConstant(8, dl, MVT::i32);
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SDValue InstrC8 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C8, DAG);
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// v1 = vror(v0,r0)
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SDValue Vror1 = getInstr(Hexagon::V6_vror, dl, VecTy, {Vor2, InstrC8}, DAG);
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// v0 = vor(v0,v1)
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SDValue Vor3 = getInstr(Hexagon::V6_vor, dl, VecTy, {Vor2, Vror1}, DAG);
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// r0 = #4 // HwLen/16
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SDValue C4 = DAG.getTargetConstant(4, dl, MVT::i32);
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SDValue InstrC4 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C4, DAG);
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// v1 = vror(v0,r0)
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SDValue Vror2 = getInstr(Hexagon::V6_vror, dl, VecTy, {Vor3, InstrC4}, DAG);
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// v0 = vor(v0,v1)
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SDValue Vor4 = getInstr(Hexagon::V6_vor, dl, VecTy, {Vor3, Vror2}, DAG);
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// The output is v.w[8]:v.w[0]
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// r3 = #0
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SDValue C0 = DAG.getTargetConstant(0, dl, MVT::i32);
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SDValue InstrC0 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C0, DAG);
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// r0 = vextract(v0,r3)
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SDValue Res =
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getInstr(Hexagon::V6_extractw, dl, MVT::i32, {Vor4, InstrC0}, DAG);
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if (VT == MVT::i64) {
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// r3 = #32
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SDValue C32 = DAG.getTargetConstant(32, dl, MVT::i32);
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SDValue InstrC32 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C32, DAG);
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// r1 = vextract(v0,r3)
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SDValue Vextract =
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getInstr(Hexagon::V6_extractw, dl, MVT::i32, {Vor4, InstrC32}, DAG);
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Res = getInstr(Hexagon::A2_combinew, dl, MVT::i64, {Vextract, Res}, DAG);
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}
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return Res;
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}
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SDValue
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HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const {
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// Sign- and zero-extends are legal.
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@ -1595,7 +1725,7 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG);
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case ISD::BITCAST: return LowerHvxBitcast(Op, DAG);
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case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG);
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case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG);
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case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG);
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26
test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll
Normal file
26
test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll
Normal file
@ -0,0 +1,26 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: danny:
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; CHECK: vand
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define i64 @danny(<64 x i8> %a0, <64 x i8> %a1) #0 {
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%v0 = icmp eq <64 x i8> %a0, %a1
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%v1 = bitcast <64 x i1> %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: sammy:
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; CHECK: vand
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define i32 @sammy(<32 x i16> %a0, <32 x i16> %a1) #0 {
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%v0 = icmp eq <32 x i16> %a0, %a1
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%v1 = bitcast <32 x i1> %v0 to i32
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ret i32 %v1
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}
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; This one still doesn't work.
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; define i16 @kirby(<16 x i32> %a0, <16 x i32> %a1) #0 {
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; %v0 = icmp eq <16 x i32> %a0, %a1
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; %v1 = bitcast <16 x i1> %v0 to i16
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; ret i16 %v1
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; }
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attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+v66,+hvx,+hvxv66,+hvx-length64b" }
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51
test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll
Normal file
51
test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll
Normal file
@ -0,0 +1,51 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that LLVM does not assert and bitcast v64i1 to i64 is lowered.
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; CHECK: v[[REG1:[0-9]+]] = valign(v{{[0-9]+}},v{{[0-9]+}},#2)
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; CHECK: v[[REG2:[0-9]+]] = vor(v{{[0-9]+}},v[[REG1]])
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; CHECK: v[[REG3:[0-9]+]] = valign(v[[REG2]],v[[REG2]],#1)
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; CHECK: v[[REG4:[0-9]+]] = vor(v{{[0-9]+}},v[[REG3]])
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; CHECK: v[[REG5:[0-9]+]] = vand(v[[REG4]],v{{[0-9]+}})
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; CHECK: v{{[0-9]+}}.w = vasl(v[[REG5]].w,v{{[0-9]+}}.w)
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target triple = "hexagon"
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define dso_local void @fun() local_unnamed_addr #0 {
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entry:
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br i1 undef, label %cleanup, label %if.end
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if.end:
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%0 = load i8, i8* undef, align 1
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%conv13.i = zext i8 %0 to i32
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%trip.count.minus.1216 = add nsw i32 %conv13.i, -1
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%broadcast.splatinsert221 = insertelement <64 x i32> undef, i32 %trip.count.minus.1216, i32 0
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%broadcast.splat222 = shufflevector <64 x i32> %broadcast.splatinsert221, <64 x i32> undef, <64 x i32> zeroinitializer
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%1 = icmp ule <64 x i32> undef, %broadcast.splat222
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%wide.masked.load223 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* nonnull undef, i32 1, <64 x i1> %1, <64 x i8> undef)
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%2 = lshr <64 x i8> %wide.masked.load223, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
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%3 = and <64 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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%4 = zext <64 x i8> %3 to <64 x i32>
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%5 = add nsw <64 x i32> undef, %4
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%6 = select <64 x i1> %1, <64 x i32> %5, <64 x i32> undef
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%bin.rdx225 = add <64 x i32> %6, undef
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%bin.rdx227 = add <64 x i32> %bin.rdx225, undef
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%bin.rdx229 = add <64 x i32> %bin.rdx227, undef
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%bin.rdx231 = add <64 x i32> %bin.rdx229, undef
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%bin.rdx233 = add <64 x i32> %bin.rdx231, undef
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%bin.rdx235 = add <64 x i32> %bin.rdx233, undef
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%bin.rdx237 = add <64 x i32> %bin.rdx235, undef
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%7 = extractelement <64 x i32> %bin.rdx237, i32 0
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%nChans = getelementptr inbounds i8, i8* null, i32 2160
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%8 = bitcast i8* %nChans to i32*
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store i32 %7, i32* %8, align 4
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br label %cleanup
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cleanup:
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ret void
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}
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; Function Attrs: argmemonly nounwind readonly willreturn
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declare <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>*, i32, <64 x i1>, <64 x i8>)
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attributes #0 = { "target-features"="+hvx-length64b,+hvxv67,+v67,-long-calls" }
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