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[X86][Btver2] Add support for multiple pipelines stages for x86 scalar schedules. NFCI.

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This allows us to use JWriteResIntPair for complex schedule classes (like WriteIDiv) as well as single pipe instructions.

llvm-svn: 327686
This commit is contained in:
Simon Pilgrim 2018-03-15 23:46:12 +00:00
parent cfe3e28072
commit e1798e5165
1 changed files with 11 additions and 22 deletions
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33
lib/Target/X86/X86ScheduleBtVer2.td
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@ -72,20 +72,20 @@ def : ReadAdvance<ReadAfterLd, 3>;
// This multiclass defines the resource usage for variants with and without
// folded loads.
multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
ProcResourceKind ExePort,
int Lat, int Res = 1, int UOps = 1> {
list<ProcResourceKind> ExePorts,
int Lat, list<int> Res = [1], int UOps = 1> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, [ExePort]> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = [Res];
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
// latency.
def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 3);
let ResourceCycles = [1, Res];
let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = UOps;
}
}
@ -116,26 +116,15 @@ def : WriteRes<WriteRMW, [JSAGU]>;
// Arithmetic.
////////////////////////////////////////////////////////////////////////////////
defm : JWriteResIntPair<WriteALU, JALU01, 1>;
defm : JWriteResIntPair<WriteIMul, JALU1, 3>;
defm : JWriteResIntPair<WriteALU, [JALU01], 1>;
defm : JWriteResIntPair<WriteIMul, [JALU1], 3>;
defm : JWriteResIntPair<WriteIDiv, [JALU1, JDiv], 41, [1, 41], 2>; // Worst case (i64 division)
def : WriteRes<WriteIMulH, [JALU1]> {
let Latency = 6;
let ResourceCycles = [4];
}
// Worst case (i64 division)
def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
let Latency = 41;
let ResourceCycles = [1, 41];
let NumMicroOps = 2;
}
def : WriteRes<WriteIDivLd, [JLAGU, JALU1, JDiv]> {
let Latency = 44;
let ResourceCycles = [1, 1, 41];
let NumMicroOps = 2;
}
// This is for simple LEAs with one or two input operands.
// FIXME: SAGU 3-operand LEA
def : WriteRes<WriteLEA, [JALU01]>;
@ -181,7 +170,7 @@ def : InstRW<[JWriteIDiv32Ld], (instrs DIV32m, IDIV32m)>;
// Integer shifts and rotates.
////////////////////////////////////////////////////////////////////////////////
defm : JWriteResIntPair<WriteShift, JALU01, 1>;
defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
def JWriteSHLDrri : SchedWriteRes<[JALU01]> {
let Latency = 3;
@ -232,7 +221,7 @@ def : WriteRes<WriteZero, []>;
// consume resources. Indirect branches can fold loads.
////////////////////////////////////////////////////////////////////////////////
defm : JWriteResIntPair<WriteJump, JALU01, 1>;
defm : JWriteResIntPair<WriteJump, [JALU01], 1>;
////////////////////////////////////////////////////////////////////////////////
// Special case scheduling classes.