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[MSSA] Add logic for special handling of atomics/volatiles.
This patch makes MemorySSA recognize atomic/volatile loads, and makes MSSA treat said loads specially. This allows us to be a bit more aggressive in some cases. Administrative note: Revision was LGTM'ed by reames in person. Additionally, this doesn't include the `invariant.load` recognition in the differential revision, because I feel it's better to commit that separately. Will commit soon. Differential Revision: https://reviews.llvm.org/D16875 llvm-svn: 277637
This commit is contained in:
George Burgess IV
parent
a2848aadf6
commit
e244b0eafa
@ -207,6 +207,50 @@ static bool lifetimeEndsAt(MemoryDef *MD, const MemoryLocation &Loc,
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return false;
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}
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enum class Reorderability {
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Always,
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IfNoAlias,
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Never
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};
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/// This does one-way checks to see if Use could theoretically be hoisted above
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/// MayClobber. This will not check the other way around.
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///
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/// This assumes that, for the purposes of MemorySSA, Use comes directly after
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/// MayClobber, with no potentially clobbering operations in between them.
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/// (Where potentially clobbering ops are memory barriers, aliased stores, etc.)
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static Reorderability getLoadReorderability(const LoadInst *Use,
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const LoadInst *MayClobber) {
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bool VolatileUse = Use->isVolatile();
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bool VolatileClobber = MayClobber->isVolatile();
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// Volatile operations may never be reordered with other volatile operations.
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if (VolatileUse && VolatileClobber)
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return Reorderability::Never;
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// The lang ref allows reordering of volatile and non-volatile operations.
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// Whether an aliasing nonvolatile load and volatile load can be reordered,
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// though, is ambiguous. Because it may not be best to exploit this ambiguity,
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// we only allow volatile/non-volatile reordering if the volatile and
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// non-volatile operations don't alias.
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Reorderability Result = VolatileUse || VolatileClobber
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? Reorderability::IfNoAlias
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: Reorderability::Always;
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// If a load is seq_cst, it cannot be moved above other loads. If its ordering
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// is weaker, it can be moved above other loads. We just need to be sure that
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// MayClobber isn't an acquire load, because loads can't be moved above
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// acquire loads.
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//
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// Note that this explicitly *does* allow the free reordering of monotonic (or
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// weaker) loads of the same address.
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bool SeqCstUse = Use->getOrdering() == AtomicOrdering::SequentiallyConsistent;
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bool MayClobberIsAcquire = isAtLeastOrStrongerThan(MayClobber->getOrdering(),
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AtomicOrdering::Acquire);
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if (SeqCstUse || MayClobberIsAcquire)
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return Reorderability::Never;
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return Result;
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}
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static bool instructionClobbersQuery(MemoryDef *MD,
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const MemoryLocation &UseLoc,
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const Instruction *UseInst,
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@ -234,6 +278,20 @@ static bool instructionClobbersQuery(MemoryDef *MD,
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ModRefInfo I = AA.getModRefInfo(DefInst, UseCS);
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return I != MRI_NoModRef;
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}
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if (auto *DefLoad = dyn_cast<LoadInst>(DefInst)) {
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if (auto *UseLoad = dyn_cast<LoadInst>(UseInst)) {
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switch (getLoadReorderability(UseLoad, DefLoad)) {
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case Reorderability::Always:
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return false;
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case Reorderability::Never:
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return true;
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case Reorderability::IfNoAlias:
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return !AA.isNoAlias(UseLoc, MemoryLocation::get(DefLoad));
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}
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}
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}
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return AA.getModRefInfo(DefInst, UseLoc) & MRI_Mod;
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}
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@ -3,6 +3,7 @@
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;
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; Ensures that atomic loads count as MemoryDefs
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; CHECK-LABEL: define i32 @foo
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define i32 @foo(i32* %a, i32* %b) {
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: store i32 4
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@ -16,3 +17,103 @@ define i32 @foo(i32* %a, i32* %b) {
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%3 = add i32 %1, %2
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ret i32 %3
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}
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; CHECK-LABEL: define void @bar
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define void @bar(i32* %a) {
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; CHECK: MemoryUse(liveOnEntry)
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; CHECK-NEXT: load atomic i32, i32* %a unordered, align 4
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load atomic i32, i32* %a unordered, align 4
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: load atomic i32, i32* %a monotonic, align 4
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load atomic i32, i32* %a monotonic, align 4
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: load atomic i32, i32* %a acquire, align 4
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load atomic i32, i32* %a acquire, align 4
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; CHECK: 3 = MemoryDef(2)
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; CHECK-NEXT: load atomic i32, i32* %a seq_cst, align 4
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load atomic i32, i32* %a seq_cst, align 4
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ret void
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}
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; CHECK-LABEL: define void @baz
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define void @baz(i32* %a) {
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: %1 = load atomic i32
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%1 = load atomic i32, i32* %a acquire, align 4
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; CHECK: MemoryUse(1)
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; CHECK-NEXT: %2 = load atomic i32, i32* %a unordered, align 4
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%2 = load atomic i32, i32* %a unordered, align 4
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: %3 = load atomic i32, i32* %a monotonic, align 4
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%3 = load atomic i32, i32* %a monotonic, align 4
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ret void
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}
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; CHECK-LABEL: define void @fences
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define void @fences(i32* %a) {
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: fence acquire
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fence acquire
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; CHECK: MemoryUse(1)
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; CHECK-NEXT: %1 = load i32, i32* %a
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%1 = load i32, i32* %a
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: fence release
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fence release
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; CHECK: MemoryUse(2)
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; CHECK-NEXT: %2 = load i32, i32* %a
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%2 = load i32, i32* %a
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; CHECK: 3 = MemoryDef(2)
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; CHECK-NEXT: fence acq_rel
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fence acq_rel
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; CHECK: MemoryUse(3)
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; CHECK-NEXT: %3 = load i32, i32* %a
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%3 = load i32, i32* %a
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; CHECK: 4 = MemoryDef(3)
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; CHECK-NEXT: fence seq_cst
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fence seq_cst
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; CHECK: MemoryUse(4)
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; CHECK-NEXT: %4 = load i32, i32* %a
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%4 = load i32, i32* %a
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ret void
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}
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; CHECK-LABEL: define void @seq_cst_clobber
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define void @seq_cst_clobber(i32* noalias %a, i32* noalias %b) {
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: %1 = load atomic i32, i32* %a monotonic, align 4
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load atomic i32, i32* %a monotonic, align 4
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: %2 = load atomic i32, i32* %a seq_cst, align 4
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load atomic i32, i32* %a seq_cst, align 4
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; CHECK: 3 = MemoryDef(2)
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; CHECK-NEXT: load atomic i32, i32* %a monotonic, align 4
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load atomic i32, i32* %a monotonic, align 4
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ret void
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}
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; Ensure that AA hands us MRI_Mod on unreorderable atomic ops.
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;
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; This test is a bit implementation-specific. In particular, it depends on that
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; we pass cmpxchg-load queries to AA, without trying to reason about them on
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; our own.
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;
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; If AA gets more aggressive, we can find another way.
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;
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; CHECK-LABEL: define void @check_aa_is_sane
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define void @check_aa_is_sane(i32* noalias %a, i32* noalias %b) {
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: cmpxchg i32* %a, i32 0, i32 1 acquire acquire
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cmpxchg i32* %a, i32 0, i32 1 acquire acquire
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; CHECK: MemoryUse(1)
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; CHECK-NEXT: load i32, i32* %b, align 4
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load i32, i32* %b, align 4
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ret void
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}
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41
test/Transforms/Util/MemorySSA/constant-memory.ll
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41
test/Transforms/Util/MemorySSA/constant-memory.ll
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@ -0,0 +1,41 @@
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; RUN: opt -basicaa -print-memoryssa -verify-memoryssa -analyze < %s 2>&1 | FileCheck %s
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;
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; Things that BasicAA can prove points to constant memory should be
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; liveOnEntry, as well.
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declare void @clobberAllTheThings()
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@str = private unnamed_addr constant [2 x i8] c"hi"
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define i8 @foo() {
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: call void @clobberAllTheThings()
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call void @clobberAllTheThings()
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%1 = getelementptr [2 x i8], [2 x i8]* @str, i64 0, i64 0
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; CHECK: MemoryUse(liveOnEntry)
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; CHECK-NEXT: %2 = load i8
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%2 = load i8, i8* %1, align 1
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%3 = getelementptr [2 x i8], [2 x i8]* @str, i64 0, i64 1
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; CHECK: MemoryUse(liveOnEntry)
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; CHECK-NEXT: %4 = load i8
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%4 = load i8, i8* %3, align 1
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%5 = add i8 %2, %4
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ret i8 %5
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}
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define i8 @select(i1 %b) {
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%1 = alloca i8, align 1
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: store i8 0
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store i8 0, i8* %1, align 1
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: call void @clobberAllTheThings()
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call void @clobberAllTheThings()
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%2 = getelementptr [2 x i8], [2 x i8]* @str, i64 0, i64 0
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%3 = select i1 %b, i8* %2, i8* %1
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; CHECK: MemoryUse(2)
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; CHECK-NEXT: %4 = load i8
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%4 = load i8, i8* %3, align 1
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ret i8 %4
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}
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30
test/Transforms/Util/MemorySSA/invariant-groups.ll
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30
test/Transforms/Util/MemorySSA/invariant-groups.ll
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@ -0,0 +1,30 @@
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; RUN: opt -basicaa -print-memoryssa -verify-memoryssa -analyze < %s 2>&1 | FileCheck %s
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;
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; Currently, MemorySSA doesn't support invariant groups. So, we should ignore
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; invariant.group.barrier intrinsics entirely. We'll need to pay attention to
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; them when/if we decide to support invariant groups.
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@g = external global i32
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define i32 @foo(i32* %a) {
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: store i32 0
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store i32 0, i32* %a, align 4, !llvm.invariant.group !0
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: store i32 1
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store i32 1, i32* @g, align 4
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%1 = bitcast i32* %a to i8*
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%a8 = call i8* @llvm.invariant.group.barrier(i8* %1)
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%a32 = bitcast i8* %a8 to i32*
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; CHECK: MemoryUse(2)
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; CHECK-NEXT: %2 = load i32
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%2 = load i32, i32* %a32, align 4, !llvm.invariant.group !0
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ret i32 %2
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}
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declare i8* @llvm.invariant.group.barrier(i8*)
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!0 = !{!"group1"}
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@ -3,6 +3,7 @@
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;
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; Ensures that volatile stores/loads count as MemoryDefs
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; CHECK-LABEL: define i32 @foo
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define i32 @foo() {
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%1 = alloca i32, align 4
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; CHECK: 1 = MemoryDef(liveOnEntry)
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@ -20,3 +21,74 @@ define i32 @foo() {
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%4 = add i32 %3, %2
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ret i32 %4
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}
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; Ensuring that we don't automatically hoist nonvolatile loads around volatile
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; loads
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; CHECK-LABEL define void @volatile_only
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define void @volatile_only(i32* %arg1, i32* %arg2) {
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; Trivially NoAlias/MustAlias
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%a = alloca i32
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%b = alloca i32
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: load volatile i32, i32* %a
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load volatile i32, i32* %a
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; CHECK: MemoryUse(liveOnEntry)
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; CHECK-NEXT: load i32, i32* %b
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load i32, i32* %b
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; CHECK: MemoryUse(1)
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; CHECK-NEXT: load i32, i32* %a
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load i32, i32* %a
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; MayAlias
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: load volatile i32, i32* %arg1
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load volatile i32, i32* %arg1
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; CHECK: MemoryUse(2)
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; CHECK-NEXT: load i32, i32* %arg2
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load i32, i32* %arg2
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ret void
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}
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; Ensuring that volatile atomic operations work properly.
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; CHECK-LABEL define void @volatile_atomics
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define void @volatile_atomics(i32* %arg1, i32* %arg2) {
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%a = alloca i32
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%b = alloca i32
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; Trivially NoAlias/MustAlias
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; CHECK: 1 = MemoryDef(liveOnEntry)
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; CHECK-NEXT: load atomic volatile i32, i32* %a acquire, align 4
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load atomic volatile i32, i32* %a acquire, align 4
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; CHECK: MemoryUse(1)
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; CHECK-NEXT: load i32, i32* %b
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load i32, i32* %b
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; CHECK: 2 = MemoryDef(1)
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; CHECK-NEXT: load atomic volatile i32, i32* %a monotonic, align 4
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load atomic volatile i32, i32* %a monotonic, align 4
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; CHECK: MemoryUse(1)
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; CHECK-NEXT: load i32, i32* %b
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load i32, i32* %b
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; CHECK: MemoryUse(1)
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; CHECK-NEXT: load atomic i32, i32* %b unordered, align 4
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load atomic i32, i32* %b unordered, align 4
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; CHECK: MemoryUse(2)
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; CHECK-NEXT: load atomic i32, i32* %a unordered, align 4
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load atomic i32, i32* %a unordered, align 4
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; CHECK: MemoryUse(2)
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; CHECK-NEXT: load i32, i32* %a
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load i32, i32* %a
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; MayAlias
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; CHECK: 3 = MemoryDef(2)
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; CHECK-NEXT: load atomic volatile i32, i32* %arg1 monotonic, align 4
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load atomic volatile i32, i32* %arg1 monotonic, align 4
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; CHECK: MemoryUse(3)
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; CHECK-NEXT: load i32, i32* %arg2
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load i32, i32* %arg2
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ret void
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}
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