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[Hexagon] Prevent a stall across zero-latency instructions in a packet

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Packetizer keeps two zero-latency bound instrctions in the same packet ignoring
the stalls on the later instruction. This should not be the case if there is no
data dependence.

Patch by Sumanth Gundapaneni.

llvm-svn: 329437
This commit is contained in:
Krzysztof Parzyszek 2018-04-06 18:13:11 +00:00
parent cbd3448493
commit e25a65a321
1 changed files with 16 additions and 15 deletions
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31
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
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@ -1807,17 +1807,18 @@ bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)]; SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
// Check if the latency is 0 between this instruction and any instruction // If the latency is 0 and there is a data dependence between this
// in the current packet. If so, we disregard any potential stalls due to // instruction and any instruction in the current packet, we disregard any
// the instructions in the previous packet. Most of the instruction pairs // potential stalls due to the instructions in the previous packet. Most of
// that can go together in the same packet have 0 latency between them. // the instruction pairs that can go together in the same packet have 0
// Only exceptions are newValueJumps as they're generated much later and // latency between them. The exceptions are
// the latencies can't be changed at that point. Another is .cur // 1. NewValueJumps as they're generated much later and the latencies can't
// instructions if its consumer has a 0 latency successor (such as .new). // be changed at that point.
// In this case, the latency between .cur and the consumer stays non-zero // 2. .cur instructions, if its consumer has a 0 latency successor (such as
// even though we can have both .cur and .new in the same packet. Changing // .new). In this case, the latency between .cur and the consumer stays
// the latency to 0 is not an option as it causes software pipeliner to // non-zero even though we can have both .cur and .new in the same packet.
// not pipeline in some cases. // Changing the latency to 0 is not an option as it causes software pipeliner
// to not pipeline in some cases.
// For Example: // For Example:
// { // {
@ -1830,10 +1831,10 @@ bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
for (auto J : CurrentPacketMIs) { for (auto J : CurrentPacketMIs) {
SUnit *SUJ = MIToSUnit[J]; SUnit *SUJ = MIToSUnit[J];
for (auto &Pred : SUI->Preds) for (auto &Pred : SUI->Preds)
if (Pred.getSUnit() == SUJ && if (Pred.getSUnit() == SUJ)
(Pred.getLatency() == 0 || HII->isNewValueJump(I) || if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
HII->isToBeScheduledASAP(*J, I))) HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))
return false; return false;
} }
// Check if the latency is greater than one between this instruction and any // Check if the latency is greater than one between this instruction and any